OVP-

LOW SIDE ON

UVP

PRE-BIASED

STARTUP CONDITION

CURRENT LIMIT

CURRENT LIMIT

DISABLE

0.8V

2.7V

Soft Start Time

`

0.8V

0.0V

`

LM20146

www.ti.com

SNVS563C – FEBRUARY 2008 – REVISED APRIL 2013

Pre-Bias Start up Capability

The LM20146 is in a pre-biased state when the device starts up with an output voltage greater than zero. This

often occurs in many multi-rail applications such as when powering an FPGA, ASIC, or DSP. In these

applications the output can be pre-biased through parasitic conduction paths from one supply rail to another.

Even though the LM20146 is a synchronous converter it will not pull the output low when a prebias condition

exists. During start up the LM20146 will not sink current until the Soft-Start voltage exceeds the voltage on the

FB pin. Since the device can not sink current it protects the load from damage that might otherwise occur if

current is conducted through the parasitic paths of the load.

Power Good and Over Voltage Fault Handling

The LM20146 has built in under and over voltage comparators that control the power switches. Whenever there

is an excursion in output voltage above the set OVP threshold, the part will terminate the present on-pulse, turn-

on the low-side FET, and pull the PGOOD pin low. The low-side FET will remain on until either the FB voltage

falls back into regulation or the zero cross detection is triggered which in turn tri-states the FETs. If the output

reaches the UVP threshold the part will continue switching and the PGOOD pin will be asserted and go low.

Typical values for the PGOOD resistor are on the order of 100 k

Ω or less. To avoid false tripping during transient

glitches the PGOOD pin has 16 µs of built in deglitch time to both rising and falling edges. The powergood

behavior for fault conditions is illustrated in Figure 27.

Figure 27. Powergood Behavior

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