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SM28VLT32SHKN датащи(PDF) 9 Page - Texas Instruments

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номер детали SM28VLT32SHKN
подробное описание детали  32-MBIT HIGH-TEMPERATURE FLASH MEMORY WITH SERIAL PERIPHERAL INTERFACE (SPI) BUS
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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SM28VLT32SHKN датащи(HTML) 9 Page - Texas Instruments

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CS#
SCK
SI
SO
Command Byte
Input Bytes (Address/Data/Dummy)
Output Data Bytes
Quick Status Byte
Dummy Output
SM28VLT32-HT
www.ti.com
SLVSAO2C – NOVEMBER 2012 – REVISED MARCH 2013
DETAILED DESCRIPTION
SERIAL COMMUNICATION
SM28VLT32 supports mode 0 and mode 3 SPI protocols. In mode 0, the inactive state of SCK is 0 whereas, in
mode 3, the state is 1. The input data on SI is always latched on rising edge of SCK and data on SO is output on
falling edge of SCK in both modes. CS# is brought low to start a new SPI data frame. The SPI data frame
consists of an 8-bit command byte followed by a variable number of bytes of input data as shown in Table 3. The
first 8 bits of SO always output the quick status bits. These bits define error conditions and status of the FLASH
(see Table 4). These bits should be evaluated after each command is executed to determine if the preceding
command completed successfully. This can be implemented as part of the SPI communication protocol with the
host device. For more information see the Application Information section. The output data on SO follows after
the complete data is provided to the device on SI pin. Invalid command bytes are ignored. Also, any additional
SCK clock cycles and additional data on SI beyond the depicted frame size are ignored. CS# going high
delineates the end of current data frame.
Figure 5. SPI Data Frame to Read, Write, Erase Memory Data and to Access Config/Status Registers
Copyright © 2012–2013, Texas Instruments Incorporated
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