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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LM3279 датащи(PDF) 3 Page - Texas Instruments |
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LM3279 датащи(HTML) 3 Page - Texas Instruments |
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3 / 37 page  Top View (Bumps Down) SCLK GPO0 GND VOUT SDATA VCON VIO FB GPO1 SW2 EN SGND SVIN PGND PVIN SW1 A B C D 1 2 3 4 LM3279 www.ti.com SNVS970C – MARCH 2013 – REVISED OCTOBER 2014 5 Pin Configuration and Functions DSBGA 16 Pins Pin Functions PIN TYPE DESCRIPTION NUMBER NAME Digital control interface (DCON) RFFE Bus clock input. Typically connected to RFFE master A1 SCLK IN on RF or Baseband IC. SCLK must be held low when VIO is not applied. Digital control interface (DCON) RFFE Bus data input/output. Typically connected to RFFE B1 SDATA I/O master on RF or Baseband IC. SDATA must be held low when VIO is not applied. Digital control interface (DCON) 1.8-V supply input. VIO functions as the RFFE interface reference voltage. VIO also functions as a reset and enable input to LM3279. Bypass C1 VIO IN capacitor should be connected between VIO and GND. Typically connected to voltage regulator controlled by RF or Baseband IC. When VIO = HIGH, EN shall be connected to GND. D1 GND Ground Digital Ground. Multipurpose GPIO. When VIO = HIGH, GPO0 is a general purpose output for configuring RF front end circuitry. When the GPO0 control bit in Register 02 is set to 1, the output is driven A2 GPO0 I/O to a 1.8-V (VIO) high logic level. The output is pulled to a low logic level when the GPO0 control bit is set to 0. (Input has an internal pull-up resistor.) Voltage Control Analog input. When EN = HIGH, VCON controls the output voltage in PWM B2 VCON IN and PFM modes. When in Digital control, VCON can be left as no connect or connected to system ground. Feedback input to inverting input of error amplifier. Connect output voltage directly to this C2 FB Ground node at load point. Regulated output voltage of LM3279. Connect this to a 10-µF ceramic output filter capacitor D2 VOUT PWR to GND. Multipurpose GPIO. When VIO = HIGH, GPO1 is a general purpose output for configuring RF front end circuitry. When the GPO1 control bit in Register 02 is set to 1, the output is driven A3 GPO1 I/O to a 1.8-V (VIO) high logic level. The output is pulled to a low logic level when the GPO1 control bit is set to 0. (Input has an internal pull-up resistor.) Enable Pin. Pulling this pin higher than 1.2 V enables part to function in analog control mode. B3 EN IN VIO must be tied to ground. C3 SGND Ground Signal Ground for analog circuits and control circuitry. Switch pin for Internal Power Switches M3 and M4. Connect inductor between SW1 and D3 SW2 PWR SW2. A4 SVIN PWR SVIN is no connect. Analog supply is internally connected to PVIN. Power MOSFET input and power current input pin. Optional low-pass filtering may help B4 PVIN PWR reduce radiated EMI and noise during buck and buck-boost modes. Switch pin for Internal Power Switches M1 and M2. Connect inductor between SW1 and C4 SW1 PWR SW2. D4 PGND Ground Power Ground for Power MOSFETs and gate drive circuitry. Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM3279 |
Аналогичный номер детали - LM3279_16 |
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Аналогичное описание - LM3279_16 |
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