SN54LV574, SN74LV574

OCTAL EDGETRIGGERED DTYPE FLIPFLOPS

WITH 3STATE OUTPUTS

SCLS199B − MARCH 1993 − REVISED APRIL 1996

1

POST OFFICE BOX 655303

POST OFFICE BOX 1443

CMOS) 2-

µ Process

MIL-STD-883C, Method 3015; Exceeds

200 V Using Machine Model

(C = 200 pF, R = 0)

Per JEDEC Standard JESD-17

Small-Outline (DW), Shrink Small-Outline

(DB), Thin Shrink Small-Outline (PW),

Ceramic Flat (W) Packages, Chip Carriers

(FK), and (J) 300-mil DIPs

description

These octal edge-triggered D-type flip-flops are

The ’LV574 feature 3-state outputs designed

specifically for driving highly capacitive or

relatively low-impedance loads. This device is

particularly suitable for implementing buffer

registers, I/O ports, bidirectional bus drivers, and

working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data

(D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the

bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines

without need for interface or pullup components.

OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

The SN74LV574 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count

and functionality of standard small-outline packages in less than half the printed-circuit-board area.

The SN54LV574 is characterized for operation over the full military temperature range of −55

°C to 125°C. The

SN74LV574 is characterized for operation from −40

°C to 85°C.

Copyright

 1996, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

EPIC is a trademark of Texas Instruments Incorporated.

32 1 20 19

910 11 1213

4

5

6

7

8

18

17

16

15

14

2Q

3Q

4Q

5Q

6Q

3D

4D

5D

6D

7D

SN54LV574 . . . FK PACKAGE

(TOP VIEW)

SN54LV574 ...J OR W PACKAGE

SN74LV574 . . . DB, DW, OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

OE

1D

2D

3D

4D

5D

6D

7D

8D

GND

1Q

2Q

3Q

4Q

5Q

6Q

7Q

8Q

CLK

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.