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MTV412MV128 датащи(PDF) 5 Page - List of Unclassifed Manufacturers

номер детали MTV412MV128
подробное описание детали  8051 Embedded Monitor Controller 128K Flash Type with ISP
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производитель  ETC [List of Unclassifed Manufacturers]
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MTV412MV128 датащи(HTML) 5 Page - List of Unclassifed Manufacturers

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MYSON-CENTURY
TECHNOLOGY
MTV412M
(Rev 0.9)
Revision 0.9
- 5 -
April 2002
FUNCTIONAL DESCRIPTIONS
1. 8051 CPU Core
The CPU core of MTV412M is compatible with the industry standard 8051, which includes 256 bytes RAM,
Special Function Registers (SFR), two timers, five interrupt sources and a serial interface. The CPU core
fetches its program code from the 128K bytes Flash in MTV412M. It uses Port0 and Port2 to access the
“external special function register” (XFR) and external auxiliary RAM (AUXRAM).
The CPU core can run at double rate when FclkE is set. Once the bit is set, the CPU runs as if a 24MHz
X’tal is applied on MTV412M, but the peripherals (IIC, DDC, H/V processor) still run at the original frequency.
Note: All registers listed in this document reside in 8051’s external RAM area (XFR). For internal RAM
memory map, please refer to 8051 spec.
2. Memory Allocation
2.1 Internal Special Function Registers (SFR)
The SFR is a group of registers that are the same as standard 8051.
2.2 Internal RAM
There are total 256 bytes internal RAM in MTV412M, the same as standard 8052.
2.3 External Special Function Registers (XFR)
The XFR is a group of registers allocated in the 8051 external RAM area F00h - FFFh. These registers are
used for special functions. Programs can use "MOVX" instruction to access these registers.
2.4 Auxiliary RAM (AUXRAM)
There are total 256 bytes auxiliary RAM allocated in the 8051 external RAM area 800h - 8FFh. Programs
can use "MOVX" instruction to access the AUXRAM.
2.5 Dual Port RAM (DDCRAM1 & DDCRAM2)
There are 2x256 bytes Dual Port RAM allocated in the 8051 external RAM area 900h - 9FFh & E00h - EFFh
for H/W auto transfer DDC. The external DDC1/2 Host can access the RAM as if two 24LC02 EEPROMs are
connected onto the interface. The HSCL1, HSDA1 pins can access DDCRAM1 directly. And the HSCL2,
HSDA2 pins can access DDCRAM2 directly. Programs can also use "MOVX" instruction to access these
RAM.
00h
7Fh
80h
FFh
Internal RAM
Accessible by
indirect
addressing only
(Using
MOV A,@Ri
instruction)
Internal RAM
Accessible by
direct and indirect
addressing
SFR
Accessible by
direct addressing
800h
8FFh
AUXRAM
Accessible by
indirect external
RAM addressing
(Using MOVX
instruction
F00h
FFFh
XFR
Accessible by
indirect external
RAM addressing
(Using MOVX
instruction)
E00h
EFFh
DDCRAM1
Accessible by
indirect external
RAM addressing
(Using MOVX
instruction)
900h
9FFh
DDCRAM2
Accessible by
indirect external
RAM addressing
(Using MOVX
instruction)


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