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TL16C2550 датащи(PDF) 4 Page - Texas Instruments

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номер детали TL16C2550
подробное описание детали  1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS
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TL16C2550-Q1
SLWS232
– DECEMBER 2011
www.ti.com
PIN FUNCTIONS (continued)
PIN
I/O
DESCRIPTION
NAME
PFB NO.
Data terminal ready (active low). These outputs are associated with individual UART channels A and
B. A logic low on these pins indicates that theTLl16C2550 is powered on and ready. These pins can
DTRA, DTRB
34, 35
O
be controlled through the modem control register. Writing a 1 to MCR bit 0 sets the DTR output to low,
enabling the modem. The output of these pins is high after writing a 0 to MCR bit 0, or after a reset.
GND
17
Signal and power ground.
Interrupt A and B (active high). These pins provide individual channel interrupts, INT A and B. INT A
and B are enabled when MCR bit 3 is set to a logic 1, interrupt sources are enabled in the interrupt
INTA, INTB
30, 29
O
enable register (IER). Interrupt conditions include: receiver errors, available receiver buffer data,
available transmit buffer space or when a modem status flag is detected. INTA-B are in the
high-impedance state after reset.
Read input (active low strobe). A high to low transition on IOR will load the contents of an internal
IOR
19
I
register defined by address bits A0-A2 onto the TL16C2550 data bus (D0-D7) for access by an
external CPU.
Write input (active low strobe). A low to high transition on IOW will transfer the contents of the data
IOW
15
I
bus (D0-D7) from the external CPU to an internal register that is defined by address bits A0-A2 and
CSA and CSB
12, 24, 25,
NC
No internal connection
37
User defined outputs. This function is associated with individual channels A and B. The state of these
pins is defined by the user through the software settings of the MCR register, bit 3. INTA-B are set to
OPA, OPB
32, 9
O
active mode and OP to a logic 0 when the MCR-3 is set to a logic 1. INTA-B are set to the 3-state
mode and OP to a logic 1 when MCR-3 is set to a logic 0. See bit 3, modem control register (MCR bit
3). The output of these two pins is high after reset.
Reset. RESET will reset the internal registers and all the outputs. The UART transmitter output and
RESET
36
I
the receiver input will be disabled during reset time. See TL16C2550 external reset conditions for
initialization details. RESET is an active-high input.
Ring indicator (active low). These inputs are associated with individual UART channels A and B. A
logic low on these pins indicates the modem has received a ringing signal from the telephone line. A
RIA, RIB
41, 21
I
low to high transition on these input pins generates a modem status interrupt, if enabled. The state of
these inputs is reflected in the modem status register (MSR)
Request to send (active low). These outputs are associated with individual UART channels A and B. A
low on the RTS pin indicates the transmitter has data ready and waiting to send. Writing a 1 in the
modem control register (MCR bit 1) sets these pins to low, indicating data is available. After a reset,
RTSA, RTSB
33, 22
O
these pins are set to high. These pins only affects the transmit and receive operation when auto RTS
function is enabled through the enhanced feature register (EFR) bit 6, for hardware flow control
operation.
Receive data input. These inputs are associated with individual serial channel data to the 2550. During
RXA, RXB
5, 4
I
the local loopback mode, these RX input pins are disabled and TX data is internally connected to the
UART RX input internally.
RXRDYA,
Receive ready (active low). RXRDY A and B goes low when the trigger level has been reached or a
31, 18
O
RXRDYB
timeout interrupt occurs. They go high when the RX FIFO is empty or there is an error in RX FIFO.
Transmit data. These outputs are associated with individual serial transmit channel data from the
TXA, TXB
7, 8
O
2550. During the local loopback mode, the TX input pin is disabled and TX data is internally connected
to the UART RX input.
TXRDYA,
Transmit ready (active low). TXRDY A and B go low when there are at least a trigger level numbers of
43, 6
O
TXRDYB
spaces available. They go high when the TX buffer is full.
VCC
42
I
Power supply inputs.
Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input. A
XTAL1
13
I
crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see
Figure 14). Alternatively, an external clock can be connected to XTAL1 to provide custom data rates.
Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal oscillator
XTAL2
14
O
output or buffered a clock output.
4
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© 2011, Texas Instruments Incorporated
Product Folder Link(s) :TL16C2550-Q1


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