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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TPS43332-Q1 датащи(PDF) 4 Page - Texas Instruments |
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TPS43332-Q1 датащи(HTML) 4 Page - Texas Instruments |
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4 / 48 page  TPS43330-Q1, TPS43332-Q1 SLVSA82F – MARCH 2011 – REVISED DECEMBER 2014 www.ti.com Pin Functions (continued) PIN I/O DESCRIPTION NAME NO. The status of this pin defines the output voltage of the boost regulator. A high input regulates the boost converter DIV 36 I at 11 V, a low input sets the value at 7 V, and a floating pin sets 10 V.(1) The capacitor at the DLYAB pin sets the power-good delay interval used to de-glitch the outputs of the power- DLYAB 21 O good comparators. Leaving this pin open sets the power-good delay to an internal default value of 20 µs typical. This input monitors the voltage on the external boost-converter low-side MOSFET for overcurrent protection. An DS 2 I alternative connection for better noise immunity is to a sense resistor between the source of the low-side MOSFET and ground via a filter network. Enable input for BuckA (active-high with an internal pullup current source). An input voltage higher than 1.7 V ENA 16 I enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and ENB are low, the device shuts down and consumes less than 4 µA of current. Enable input for BuckB (active-high with an internal pullup current source). An input voltage higher than 1.7 V ENB 17 I enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and ENB are low, the device shuts down and consumes less than 4 µA of current.(1) This input enables and disables the boost regulator. An input voltage higher than 1.7 V enables the controller. Voltages lower than 0.7 V disable the controller. Because this pin provides an internal pulldown resistor (500 k Ω), ENC 19 I enabling the boost function requires pulling it high. When enabled, the controller starts switching as soon as VBAT falls below the boost threshold, depending upon the programmed output voltage. One can use EXTSUP to supply the VREG regulator from one of the TPS43330-Q1 or TPS43330-Q2 buck EXTSUP 37 I regulator rails to reduce power dissipation in cases where there is an expectation of high VIN. If EXTSUP is unused, leave the pin open without a capacitor installed. Feedback voltage pin for BuckA. The buck controller regulates the feedback voltage to the internal reference of FBA 12 I 0.8 V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output voltage. Feedback voltage pin for BuckB. The buck controller regulates the feedback voltage to the internal reference of FBB 27 I 0.8 V. A suitable resistor-divider network between the buck output and the feedback pin sets the desired output voltage. This output can drive the external high-side N-channel MOSFET for buck regulator BuckA. The output provides GA1 6 O high peak currents to drive capacitive loads. The gate-drive reference is to a floating ground provided by PHA that has a voltage swing provided by CBA. This output can drive the external low-side N-channel MOSFET for buck regulator BuckA. The output provides GA2 8 O high peak currents to drive capacitive loads. VREG provides the voltage swing on this pin. This output can drive the external high-side N-channel MOSFET for buck regulator BuckB. The output provides GB1 33 O high peak currents to drive capacitive loads. The gate-drive reference is to a floating ground provided by PHB that has a voltage swing provided by CBB. This output can drive the external low-side N-channel MOSFET for buck regulator BuckB. The output provides GB2 31 O high peak currents to drive capacitive loads. VREG provides the voltage swing on this pin. This output can drive an external low-side N-channel MOSFET for the boost regulator. This output provides high GC1 3 O peak currents to drive capacitive loads. VREG provides the voltage swing on this pin. This pin makes a floating output drive available to control the external P-channel MOSFET. This MOSFET can GC2 4 O bypass the boost rectifier diode or a reverse-protection diode when the boost status is non-switching or disabled, and thus reduce power losses. Open-drain power-good indicator pin for BuckA. An internal power-good comparator monitors the voltage at the PGA 15 O feedback pin and pulls this output low when the output voltage falls below 93% of the set value, or if either VIN or VBAT drops below the respective undervoltage threshold. Open-drain power-good indicator pin for BuckB. An internal power-good comparator monitors the voltage at the PGB 24 O feedback pin and pulls this output low when the output voltage falls below 93% of the set value, or if either VIN or VBAT drops below the respective undervoltage threshold. PGNDA 9 O Power ground connection to the source of the low-side N-channel MOSFETs of BuckA PGNDB 30 O Power ground connection to the source of the low-side N-channel MOSFETs of BuckB Switching terminal of buck regulator BuckA, providing a floating ground reference for the high-side MOSFET gate- PHA 7 O driver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired. Switching terminal of buck regulator BuckB, providing a floating ground reference for the high-side MOSFET gate- PHB 32 O driver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired. Connecting a resistor to ground on this pin sets the operational switching frequency of the buck and boost RT 22 O controllers. A short circuit to ground on this pin defaults operation to 400 kHz for the buck controllers and 200 kHz for the boost controller. (1) DIV = high and ENC = high inhibits low-power mode on the bucks. 4 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: TPS43330-Q1 TPS43332-Q1 |
Аналогичный номер детали - TPS43332-Q1 |
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Аналогичное описание - TPS43332-Q1 |
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