S5

PGOOD

VREF

0.9 V

10 mA

VTT

0.9 V

2 A

TPS51116RGE

20

19

18

17

VBST

DRVH

LL

DRVL

V5FILT

VLDOIN

VTTGND

VTTSNS

7

8

VTT

CS_GND

9

10

VDDQSET

CS

VDDQSNS

16

15

14

13

PGOOD

12

11

S5

S3

GND

MODE

VTTREF

COMP

NC

NC

V5IN

PGND

22

21

24

23

1

2

3

4

5

6

C1

5V_IN

VDDQ

1.8 V

10 A

VIN

M1

M2

S3

L1

IRF7832

IRF7821

C4

C3

Ceramic

2y10 µF

Ceramic

0.033

µF

Ceramic

0.1

µF

1

µH

C6

SP−CAP

2y150 µF

C5

Ceramic

2y10 µF

C2

Ceramic

1

µF

C7

Ceramic

1

µF

R2

100 k

Ω

R1

5.1 k

Ω

R3

5.1

Ω

UDG−04153

TI Information — Selective Disclosure

TPS51116

www.ti.com

SLUS609I – MAY 2004 – REVISED JANUARY 2014

Complete DDR, DDR2, DDR3, and LPDDR3 Memory Power Solution

Synchronous Buck Controller, 3-A LDO, Buffered Reference

Check for Samples: TPS51116

1

FEATURES

DESCRIPTION

The TPS51116 provides a complete power supply for

2

•

Synchronous Buck Controller (VDDQ)

DDR/SSTL-2, DDR2/SSTL-18, DDR3/SSTL-15, and

–

Wide-Input Voltage Range: 3.0-V to 28-V

LPDDR3

memory

systems.

It

integrates

a

–

D

−CAP™ Mode with 100-ns Load Step

synchronous buck controller with a 3-A sink/source

Response

tracking linear regulator and buffered low noise

reference. The TPS51116 offers the lowest total

–

Current Mode Option Supports Ceramic

solution cost in systems where space is at a

Output Capacitors

premium. The TPS51116 synchronous controller runs

–

Supports Soft-Off in S4/S5 States

fixed 400-kHz, pseudo-constant frequency PWM with

–

an adaptive on-time control that can be configured in

D-CAP™ Mode for ease of use and fastest transient

–

2.5-V (DDR), 1.8-V (DDR2), Adjustable to

response or in current mode to support ceramic

1.5-V (DDR3) or 1.2-V (LPDDR3) or

output

capacitors.

The

3-A

sink/source

LDO

Output Range 0.75-V to 3.0-V

maintains fast transient response only requiring 20-

μF

–

Equipped with Powergood, Overvoltage

(2 × 10

μF) of ceramic output capacitance. In

Protection and Undervoltage Protection

addition, the LDO supply input is available externally

to significantly reduce the total power losses. The

•

3-A LDO (VTT), Buffered Reference (VREF)

TPS51116 supports all of the sleep state controls

–

Capable to Sink and Source 3 A

placing VTT at high-Z in S3 (suspend to RAM) and

–

LDO Input Available to Optimize Power

discharging VDDQ, VTT and VTTREF (soft-off) in

Losses

S4/S5 (suspend to disk). TPS51116 has all of the

protection features including thermal shutdown and is

–

Requires only 20-

μF Ceramic Output

offered in both a 20-pin HTSSOP PowerPAD™

Capacitor

package and 24-pin 4×4 QFN.

–

Buffered Low Noise 10-mA VREF Output

–

Accuracy ±20 mV for both VREF and VTT

APPLICATIONS

–

Supports High-Z in S3 and Soft-Off in S4/S5

•

DDR/DDR2/DDR3/LPDDR3 Memory Power

–

Thermal Shutdown

Supplies

•

SSTL-2, SSTL-18, SSTL-15 and HSTL

Termination

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

D-CAP, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Copyright © 2004–2014, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.