3.4.1 Initialization and Reset

Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from

NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initializa-

tion period is complete. No clocks will be generated until the initialization is complete. There are two types of resets available. A hard

reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be re-

stored to their initial state including the serial interface. A hard reset is initiated using the RSTb pin or by asserting the hard reset bit. A

soft reset bypasses the NVM download. It is simply used to initiate register configuration changes. A hard reset affects all DSPLLs,

while a soft reset can either affect all or each DSPLL individually.

No valid

input clocks

selected

Lock Acquisition

(Fast Lock)

Locked

Mode

Holdover

Mode

Phase lock on

selected input

clock is achieved

An input is

qualified and

available for

selection

No valid input

clocks available

for selection

Free-run

Valid input clock

selected

Reset and

Initialization

Power-Up

Selected input

clock fails

Yes

No

Holdover

History

Valid?

Other Valid

Clock Inputs

Available?

No

Yes

Input Clock

Switch

Figure 3.1. Modes of Operation

3.4.2 Free-run Mode

Once power is applied to the Si5348 and initialization is complete, all three DSPLLs will automatically enter freerun mode. The frequen-

cy accuracy of the generated output clocks in freerun mode is entirely dependent on the frequency accuracy of the clock source at the

reference inputs (REF/REFb). A TCXO or OCXO is recommended for applications that need frequency accuracy and stability to meet

the synchronization standards as shown in the following table:

Table 3.2. Free-run Accuracy for North American and European Synchronization Standards

SONET (Telcordia)

SDH (ITU-T)

SyncE (ITU-T)

Free-run Accuracy

GR-253 Stratum 3E

G.812 Type III

—

±4.6 ppm

GR-253 Stratum 3

G.812 Type IV

G.8262 EEC Option 2

—

G.813 Option 1

G.8262 EEC Option 1

3.4.3 Lock Acquisition Mode

Each of the DSPLLs independently monitors its configured inputs for a valid clock. If at least one valid clock is available for synchroni-

zation, a DSPLL will automatically start the lock acquisition process.If the fast lock feature is enabled, a DSPLL will acquire lock using

the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. Dur-

ing lock acquisition the outputs will generate a clock that follows the VCO frequency change as it pulls-in to the input clock frequency.

Si5348 Rev D Data Sheet

Functional Description

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