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FAN5068MPX датащи(PDF) 4 Page - Fairchild Semiconductor |
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FAN5068MPX датащи(HTML) 4 Page - Fairchild Semiconductor |
4 / 18 page PRODUCT SPECIFICATION FAN5068 4 REV. 1.0.1 9/9/04 Figure 3. VTT Regulator Block Diagram Pin Configuration FAN5068MP 5x5 mm MLP-24 Package ( θ JA = 38°C/W, θJC = 1.4°C/W)* Note: Connect P1 pad to GND. Pin Definitions Pin # Pin Name Pin Function Description 1 G1.2 Gate Drive for the 1.2V LDO. Turned off (low) in S3 and S5 modes. 2 FB1.2 Feedback for the 1.2V LDO Output. Tie to a voltage higher than 0.9V to disable this regulator. 3 SBSW Standby Switch. Drives the P-Channel MOSFET to power 5V DUAL from 5VSB when in S3. Goes high in S0 and S5. 4 5V MAIN 5V MAIN. When this pin is below 4.5V, transition from S3 to S0 is inhibited. 5 VTT SNS VTT Remote Sense Input. 6 VTT OUT VTT Regulator Power Output. 7 VDDQ IN VDDQ Input from PWM. Connect to PWM output voltage. This is the VTT Regulator power input. VTT SNS VTT OUT – + EN S3 VDDQ IN PGND REF IN VDDQ IN 50K 50K R9 R10 78 9 10 11 12 24 23 22 21 20 19 EN S3#I S3#O 3.3 ALW VCC PGOOD 1 2 3 4 5 6 18 17 16 15 14 13 G1.2 FB1.2 SBSW 5V MAIN VTT SNS VTT OUT P1 = GND *Test method as per JEDEC Specification JESD51-5 |
Аналогичный номер детали - FAN5068MPX |
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Аналогичное описание - FAN5068MPX |
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