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ES1030QI датащи(PDF) 8 Page - Altera Corporation |
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ES1030QI датащи(HTML) 8 Page - Altera Corporation |
8 / 14 page ES1030QI Nested Sequencing For many integrated circuits with multiple power supply domains, the manufacturer establishes a prescribed voltage sequencing order for both power- up and power-down. The sequencing order ensures the safety of the device and prevents potentially damaging currents from flowing from one power domain to another through parasitic junctions in the device. The ES1030QI uses the most common pattern of sequencing, nested sequencing, where power domains are activated in a certain order (such as 1-2-3-4) and then removed in the reverse order (4- 3-2-1). Nested sequencing is illustrated in the waveforms shown in Figures 5 through 7. Four-Channels with Qualification Window The ES1030QI allows nested sequencing of four power channels per ES1030QI device. After the master enable (EN) signal goes high to start the sequence, each output enable (OEx) signal transitions high in the prescribed 1-2-3-4 order. A resistor divider from the REF_O output to the ACNTL input pin determines a precision time delay between successive OEx outputs. During this time delay, or qualification window, the ES1030QI pauses for a transition of the PGx signal corresponding to the OEx signal to indicate the enabled power supply has a valid output. Successive outputs are enabled with the same qualification window. The power supplies are sequenced down in the reverse order if any of these events are true: 1. Negation of the EN signal. 2. Failure of any PGx to become true within its corresponding qualification window. 3. Any other fault (such as from chained ES1030QI parts) introduced into the nFAULT_IN input. This input is negative logic to allow open-drain wired OR configurations. Precision Delay Unlike other sequencing solutions which rely on poorly-specified current sources and wide-tolerance capacitors, the ES1030QI generates a precision delay using precision resistors and mixed-signal techniques. An internal reference produces an output voltage which sources 1.05 V on the REF_O pin. The voltage divider you select from REF_O divides the voltage to any value between 20 mV and 1.05 V. The divider impedance (R1+R2) should be kept >100k ohms for accurate delay settings. The ACNTL pin samples the divided voltage with an internal analog to digital (A/D) converter. The resulting digital value is the divider for an internal clock, resulting in a precision time delay. The delay is scaled to range from 33 μs to 8.04 ms according to the formula: Tdelay=(N/255)*8.04ms, where N=(Vacntl/1.05V)*255 quantized to 8-bit values (0-255) To limit the potential timing error to less than 20% of the set value, delays for N=5 or less should not be used. The delay time is the same for all intervals between successive outputs, and for both sequence up and sequence down directions. Chaining Functions Use the ES1030QI in multiple instances to extend the number of power rails sequenced up to at least 16 rails. You can accomplish this by connecting the NEXT_O, NEXT_IN, EN, OE_O, nFAULT_O, nFAULT_IN, and ALL_PG signals as shown in the chaining application circuit in Figure 4. This connection extends the behavior of the nested sequencing function to an additional four channels per each ES1030QI added to the chain. Each ES1030QI has its own time delay generator, and the delay values do not need to be the same for all instances of the part. Convenience Logic Functions The ES1030QI allows additional logic functions to make system application of the part much easier. Since the individual regulator PGx signals must remain distinct to satisfy the qualification windows during sequencing, an additional signal ALL_PG is introduced as the logical AND of the individual PGx signals. The nFAULT_IN signal is a negative logic signal driven by the open-drain nFAULT_O signal, allowing connection to other open-drain nFAULT signals on the same connection. With this connection, other recognized faults in the system can trigger the system to sequence down in an orderly way. The negative logic (nFAULT_O) signal asserts when the qualification windows for any of the PGx signals fail. In addition to its function as a chaining signal, OE_O going LOW indicates that the sequence down 8 www.altera.com/enpirion |
Аналогичный номер детали - ES1030QI |
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Аналогичное описание - ES1030QI |
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