Common I/O SigmaDDR-II+ Burst of 2 SRAM Truth Table

LD

R/W

DQ

Operation

A + 0

A + 1

↑

1

X

Hi-Z / *

Hi-Z / *

Deselect

↑

0

0

Write

↑

0

1

Read

Notes:

1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”.

2. D1 and D2 indicate the first and second pieces of Write Data transferred during Write operations.

3. Q1 and Q2 indicate the first and second pieces of Read Data transferred during Read operations.

4. When On-Die Termination is disabled (ODT = 0), DQ drivers are disabled (i.e., DQ pins are tri-stated) for one cycle in response to NOP

and Write commands, 2.5 cycles after the command is sampled.

5. When On-Die Termination is enabled (ODT = 1), DQ drivers are disabled for one cycle in response to NOP and Write commands, 2.5

cycles after the command is sampled. The state of the DQ pins during that time (denoted by “*” in the table above) is determined by the

state of the DQ input termination. See the Input Termination Impedance Control section for more information.

Burst of 2 Byte Write Clock Truth Table

BW

BW

Current Operation

D

D

K

↑

K

↑

K

↑

K

↑

K

↑

T

T

Write

Dx stored if BWn = 0 in both data transfers

D1

D2

T

F

Write

Dx stored if BWn = 0 in 1st data transfer only

D1

X

F

T

Write

Dx stored if BWn = 0 in 2nd data transfer only

X

D2

F

F

Write Abort

No Dx stored in either data transfer

X

X

Notes:

1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.

2. If one or more BWn = 0, then BW = “T”, else BW = “F”.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.00b 11/2011

9/29

© 2011, GSI Technology

GS81302TT06/11/20/38E-500/450/400/350