поискавой системы для электроныых деталей |
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TC55V040AFT-55 датащи(PDF) 8 Page - Toshiba Semiconductor |
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TC55V040AFT-55 датащи(HTML) 8 Page - Toshiba Semiconductor |
8 / 11 page TC55V040AFT-55,-70 2003-08-06 8/11 Note: (1) R/W remains HIGH for the read cycle. (2) If CE1 goes LOW(or CE2 goes HIGH) coincident with or after R/W goes LOW, the outputs will remain at high impedance. (3) If CE1 goes HIGH(or CE2 goes LOW) coincident with or before R/W goes HIGH, the outputs will remain at high impedance. (4) If OE is HIGH during the write cycle, the outputs will remain at high impedance. (5) Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. DATA RETENTION CHARACTERISTICS (Ta = −40° to 85°C) SYMBOL PARAMETER MIN TYP MAX UNIT VDH Data Retention Supply Voltage 1.5 3.6 V Ta = −40~40°C 1 VDH = 3.0 V Ta = −40~85°C 5 IDDS2 Standby Current VDH = 3.6 V Ta = −40~85°C 7 µA tCDR Chip Deselect to Data Retention Mode Time 0 ns tR Recovery Time tRC (See Note) ns Note: Read cycle time CONTROLLED DATA RETENTION MODE (See Note 1) CE2 CONTROLLED DATA RETENTION MODE (See Note 3) CE1 2.7 V GND VIH DATA RETENTION MODE TR (See Note 2) (See Note 2) tCDR VDD − 0.2 V 1 CE VDD VDD VDD 2.7 V GND VIL DATA RETENTION MODE tR tCDR 0.2 V VIH CE2 VDD |
Аналогичный номер детали - TC55V040AFT-55 |
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Аналогичное описание - TC55V040AFT-55 |
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