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DM336P датащи(PDF) 9 Page - List of Unclassifed Manufacturers |
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DM336P датащи(HTML) 9 Page - List of Unclassifed Manufacturers |
9 / 40 page DM336P V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set Final 9 Version: DM336P-DS-F02 August 15, 2000 d. Modem Output Port Register: Address D000H Write only bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 PO0 SEL2 SEL1 /POR These 4 bits work as output ports in response to the 88th, 89th, 90th and 47th pins of this chip (see pin description). e. PnP Isolation & Resource Data Port: Address F800H Write only The PnP isolation and resource data can be byte- sequentially written to the corresponding memory (built-in SRAM) through this register. f. Auto-configuration Register: Address F400H bit2 bit1 bit0 IRQ bit5 bit4 bit3 I/O 0 0 0 3 0 0 0 03F8-03FF(COM1) 0 0 1 4 0 0 1 02F8-02FF(COM2) 0 1 0 5 0 1 0 03E8-03EF(COM3) 0 1 1 7 0 1 1 02E8-02EF(COM4) 1 0 0 10 1 0 0 03F0-03F7(COM5) 1 0 1 11 1 0 1 02F0-02F7(COM6) 1 1 0 12 1 1 0 03E0-03E7(COM7) 1 1 1 15 1 1 1 02E0-02E7(COM8) The default I/O base and IRQ data stored in 94C46 should be loaded to this register by micro-controller, and then enable the default configuration. Micro- controller can also get the current I/O base and IRQ information by a read from this register. The configuration determined by this register should be disabled when the register detects the Initiation Key described in the next section. Bit 6: When this bit is set to inform micro-controller that the current I/O base and IRQ data should be stored to 93C46 as the default setting at the next power-on reset through programming the Auto-configuration Register, this bit should be cleared by micro-controller. Bit 7: When bit 7 is set, it enables hardware configuration set according to bit 0-bit 5 (Jumper mode) and load the proper value of PnP Registers including I/O and Interrupt Configuration Registers. This bit will be reset, when it receives PnP Initial Key sequence. * When reset condition occurred, the I/O and Interrupt configuration registers must be reset to default value according to bit 0 - bit 5. 4. UART(16550A) Emulation Registers a. Receiver Buffer (Read), Transmitter Holding Register (Write) Address: 0 (DLAB=0) Reset State 00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 When this register address is read, it contains the parallel received data. Data to be transmitted is written to this register. b. Interrupt Enable Register (IER): Address 1 Reset State 00h, Write Only bit7 bit6 bit 5 bit4 bit3 bit2 bit1 bit0 0 0 0 0 Enable Mode mStatu s Intr Enable Line Status Intr Enable TX Holdin g Regist er Intr Enable RX Data Intr This 8-bit register enables the four types of interrupts as described below. Each interrupt source can activate the INT output signal if enabled by this register. Resetting bits 0 through 3 will disable all UART interrupts. Bit 0: This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic 1. Bit 1: This bit enables the Transmitter Holding Register Empty Interrupt when set to logic 1. Bit 2: This bit enables the Receiver Line Status Interrupt when set to logic 1. Bit 3: This bit enables the MODEM Status Interrupt when set to logic 1. Bit 4-7: Not used |
Аналогичный номер детали - DM336P |
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Аналогичное описание - DM336P |
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