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TSZ02201-0H5H0B301770-1-2

© 2016 ROHM Co., Ltd. All rights reserved.

25.Apr.2016 Rev.002

www.rohm.com

TSZ22111

• 15 • 001

BD16933EFV-C

Operation of Each Block

1. Serial Peripheral Interface: SPI

CSB

SDI

SCK

SDO

( TER=0 )

MSB

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

LSB

0

MSB

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

LSB

0

SDO

( TER=1 )

All "High"

X

X

X：Unstable state

TER (Internal signal) :

” 0 ” in normal operation / ” 1 ” in detecting erroneous SPI transmission

16bit serial interface is equipped to control ON / OFF of driver and various protections as well as to read out the state of

protections. Input / Output register and its functions are described below.

(1) Input Data Register

Bit

Number

Name

Description

Bit Status

Initial

Value

15

SRR

Status Reset Register

( This bit will self clear )

0 : Normal

1 : Reset

0

14

HSC1

Control High side 1

0 : High side Off

1 : High side On

0

13

LSC1

Control Low side 1

0 : Low side Off

1 : Low side On

0

12

HSC2

Control High side 2

0 : High side Off

1 : High side On

0

11

LSC2

Control Low side 2

0 : Low side Off

1 : Low side On

0

10

HSC3

Control High side 3

0 : High side Off

1 : High side On

0

9

LSC3

Control Low side 3

0 : Low side Off

1 : Low side On

0

8

-

Not Used

-

0

7

-

Not Used

-

0

6

-

Not Used

-

0

5

-

Not Used

-

0

4

-

Not Used

-

0

3

UNDER

LOAD

Under Loads Register Mode

0 :ON

1 : OFF

0

2

TSDSTH

TSDS Register Mode

0 : Latch

1 : Through

0

1

PSSTH

OVPS / UVLOS Register Mode

0 : Latch

1 : Through

0

0

RESERVE

RESERVE

0 : Normal

1 : Prohibit

0

Input of High Side ON and Low Side ON via SPI control is prohibited. The input of High Side ON and Low Side ON

results in High Side OFF and Low Side ON state.

Daisy chain is not recommended due to its reliability concern. Connect Chip Select (CSB) to each device and run by SPI

parallel control instead.

Figure 11. SPI Communication Format