CAT24C64BC4, CAT24C64BAC4

www.onsemi.com

5

Figure 4. Acknowledge Timing

18

9

START

SCL FROM

MASTER

BUS RELEASE DELAY (TRANSMITTER)

BUS RELEASE DELAY (RECEIVER)

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

ACK SETUP (

ACK DELAY (

Figure 5. Bus Timing

SCL

SDA IN

SDA OUT

WRITE OPERATIONS

Byte Write

To write data to memory, the Master creates a START

condition on the bus and then broadcasts a Slave address

with the R/W bit set to ‘0’. The Master then sends two

address bytes and a data byte and concludes the session by

creating a STOP condition on the bus. The Slave responds

with ACK after every byte sent by the Master (Figure 6). The

STOP starts the internal Write cycle, and while this

and the Slave does not acknowledge the Master (Figure 7).

Page Write

The Byte Write operation can be expanded to Page Write,

by sending more than one data byte to the Slave before

issuing the STOP condition (Figure 8). Up to 32 distinct data

bytes can be loaded into the internal Page Write Buffer

starting at the address provided by the Master. The page

address is latched, and as long as the Master keeps sending

data, the internal byte address is incremented up to the end

of page, where it then wraps around (within the page). New

data can therefore replace data loaded earlier. Following the

STOP, data loaded during the Page Write session will be

Acknowledge Polling

As soon (and as long) as internal Write is in progress, the

Slave will not acknowledge the Master. This feature enables

the Master to immediately follow−up with a new Read or

Write request, rather than wait for the maximum specified

response from the Slave, the Master simply repeats the

request until the Slave responds with ACK.

Delivery State

The CAT24C64BC4/CAT24C64BAC4 is shipped erased,

i.e., all bytes are FFh.