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CAT25M02DTR датащи(PDF) 8 Page - ON Semiconductor |
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CAT25M02DTR датащи(HTML) 8 Page - ON Semiconductor |
8 / 14 page CAT25M02 www.onsemi.com 8 Byte Write Once the WEL bit is set, the user may execute a write sequence, by sending a WRITE instruction, a 24−bit address and a data byte as shown in Figure 5. Only 18 significant address bits are used by the CAT25M02. The rest are don’t care bits, as shown in Table 10. Internal programming will start after the low to high CS transition. During an internal write cycle, all commands, except for RDSR (Read Status Register) will be ignored. The RDY bit will indicate if the internal write cycle is in progress (RDY high), or the device is ready to accept commands (RDY low). Page Write After sending the first data byte to the CAT25M02, the host may continue sending data, up to a total of 256 bytes, according to timing shown in Figure 6. After each data byte, the lower order address bits are automatically incremented, while the higher order address bits (page address) remain unchanged. If during this process the end of page is exceeded, then loading will “roll over” to the first byte in the page, thus possibly overwriting previoualy loaded data. Following completion of the write cycle, the CAT25M02 is automatically returned to the write disable state. Write Identification Page The additional 256-byte Identification Page (IP) can be written with user data using the same Write commands sequence as used for Page Write to the main memory array (Figure 6). The IPL bit from the Status Register must be set (IPL = 1) using the WRSR instruction, before attempting to write to the IP. Prior to any write to the Identification Page, the Write Enable Latch must be set (WEL=1) by sending the WREN instruction. The address bits [A23:A8] are Don’t Care and the [A7:A0] bits define the byte address within the Identification Page. In addition, the Byte Address must point to a location outside the protected area defined by the BP1, BP0 bits from the Status Register. When the full memory array is write protected (BP1, BP0 = 1,1), the write instruction to the IP is not accepted and not executed. Also, the write to the IP is not accepted if the LIP bit from the Status Register is set to 1 (the page is locked in Read-only mode). Table 10. BYTE ADDRESS Device Address Significant Bits Address Don’t Care Bits # Address Clock Pulses Main Memory Array A17 − A0 A23 – A18 24 Identification Page A7 − A0 A23 – A8 24 Figure 5. Byte WRITE Timing SCK SI SO 00 00 00 10 D7 D6 D5 D4 D3 D2 D1 D0 0 1 2 3 4 5 6 7 8 29 30 313233 34 35363738 39 OPCODE DATA IN HIGH IMPEDANCE BYTE ADDRESS* Note: Dashed Line = mode (1, 1) * Please check the Byte Address Table (Table 10) CS AN A0 SCK SI SO 00 0 0 00 1 0 BYTEADDRESS* Data Byte 1 012345678 29 30 31 32−39 40−47 Data Byte 2 Data Byte N OPCODE 7..1 0 32+(N−1)x8−1....32+(N−1)x8 32+Nx8−1 DATA IN HIGH IMPEDANCE Note: Dashed Line = mode (1, 1) Figure 6. Page WRITE Timing * Please check the Byte Address Table (Table 10) CS AN A0 |
Аналогичный номер детали - CAT25M02DTR |
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Аналогичное описание - CAT25M02DTR |
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