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6V49205BNLGI8 датащи(PDF) 8 Page - Integrated Device Technology |
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6V49205BNLGI8 датащи(HTML) 8 Page - Integrated Device Technology |
8 / 16 page FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY 8 REVISION R 11/23/16 6V49205B DATASHEET Electrical Characteristics - REF(5:0) Electrical Characteristics - USB_CLK(2:1) Electrical Characteristics - 2.048M(1:0) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Clock Frequency f VT = OVDD/2 V MHz 2,3 Crystal Frequency Error ppm Including all aging and tuning effects -50 50 ppm 1,2 Output High Voltage VOH VOH at the selected operating frequency 2.2 V 1 Output Low Voltage VOL VOL at the selected operating frequency 0.4 V 1 Slew Rate VDDO 3 3V tSLEW '00' = Hi-Z 1.0 1.7 2.7 V/ns 1,3,4 Duty Cycle dt1 VT = OVDD/2 V 40 51 60 % 1 Pin to Pin Skew tskew VT = 1.5 V, odd/even outputs have an intentional 180degree phase shift. ps 1 Jitter, Peak period jitter tjpeak VT = OVDD/2 V ±78 ±200 ps 1 Jitter, Phase tjphase (12kHz-5MHz), VT = 1.5 V 1.7 3 ps rms 1 N/A 25.00 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES MHz 2,3 MHz 2,3 Synthesis error ppm ppm 1,2,5 Output High Voltage VOH VOH at the selected operating frequency 2.2 V 1 Output Low Voltage VOL VOL at the selected operating frequency 0.4 V 1 tSLEW00 '00' = Hi-Z V/ns tSLEW01 '01' Slow Slew Rate (Averaging on) 1.0 1.4 1.8 V/ns 1,3,4 tSLEW10 '10' Fast Slew Rate (Averaging on) 1.5 2.0 2.7 V/ns 1,3,4 tSLEW11 '11' Fastest Slew Rate (Averaging on) 1.8 2.3 3.1 V/ns 1,3,4 Duty Cycle dt1 VT = OVDD/2 V 45 50.3 55 % 1 Jitter, RMS tjRMS 12kHz to Nyquist 23 120 ps 1 Jitter, Cycle to cycle tjcyc-cyc VT = OVDD/2 V 142 350 ps 1 Slew Rate VDDO = 3.3V Hi-Z 24.00 0 Clock Frequency fUSB_CLK VT = OVDD/2 V 12.00 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Clock Frequency fUSB_CLK VT = OVDD/2 V MHz 2,3,6 Synthesis error ppm ppm 1,2,5 Output High Voltage VOH VOH at the selected operating frequency 2.2 V 1 Output Low Voltage VOL VOL at the selected operating frequency 0.4 V 1 tSLEW00 '00' = Hi-Z V/ns tSLEW01 '01' Slow Slew Rate (Averaging on) 1.1 1.7 2.5 V/ns 1,3,4 tSLEW10 '10' Fast Slew Rate (Averaging on) 1.6 2.3 3.2 V/ns 1,3,4 tSLEW11 '11' Fastest Slew Rate (Averaging on) 1.8 2.6 3.6 V/ns 1,3,4 Duty Cycle dt1 VT = OVDD/2 V 45 46.7 55 % 1 Pin to Pin Skew tskew VT = OVDD/2 V 108 250 ps 1 Jitter, RMS tjRMS 12kHz to Nyquist 47 70 ps 1 Jitter, Peak period jitter tjpeak VT = OVDD/2 V ±170 ±250 ps 1 Notes for single-ended clocks: 1 Guaranteed by design and characterization, not 100% tested in production. 2 Clock Frequency specifications are guaranteed assuming that REF is at 25MHz 3 At default SMBus settings 4 Measured betweeen 20% and 80% of OVDD 5 This is the frequency error with respect to the crystal frequency. 6 Measured at the rising and/or falling edge at OVDD/2 V. 7 Phase noise is calculated as the FFT of the TIE jitter. 8 Slew rate is measured from ±0.3ΔVAC at the center of peak to peak voltage at the clock input. Hi-Z Slew Rate VDDO = 3.3V 2.048 0 |
Аналогичный номер детали - 6V49205BNLGI8 |
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Аналогичное описание - 6V49205BNLGI8 |
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