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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LM2650MX-ADJ датащи(PDF) 7 Page - National Semiconductor (TI) |
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LM2650MX-ADJ датащи(HTML) 7 Page - National Semiconductor (TI) |
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7 / 11 page  Operation OVERVIEW The LM2650 uses two step-down conversion modes: fixed-frquency pulse-width modulation (PWM) and hyster- etic. It moves freely and automatically between them, using PWM for moderate to heavy loads and hysteretic for light loads. For clarity, separate block diagrams for each conversion mode have been included. See Figure 1 and Figure 2. Blocks used in both modes appear in both diagrams with the same label. For example, both modes use the input buffer B. To keep the diagrams simple, most power supply rails have been omitted. R3, C10, R C,CC,CB, L1, R1, R2, and COUT are outside the IC. THE PWM CIRCUIT ( Figure 1) The PWM is a fixed-frequency, voltage-mode pulse-width modulator. It consists of four functional blocks: an input buffer, an error amplifier, a modulator, and a power stage. 1. The input buffer B: B is a voltage follower. A fraction of the output voltage is fed back to its noninverting input FB. Circumventing B by using the COMP input as the feedback input will cause the IC to malfunction. 2. The error amplifier EA: EA is a voltage amplifier. It subtracts the feedback voltage from the 1.25V reference and amplifies the difference to produce an error voltage for the control loop. For the purpose of loop compensa- tion, EA is typically configured as an integrator. In this configuration, a capacitor C C and a resistor RC are connected in series between the inverting input COMP and the output terminal EA OUT. The capacitor and the internal 6.5k Ω resistor create a pole, while the capacitor and series resistor create a zero. 3. The modulator: The modulator is the heart of the PWM circuit. It consists of the 90 kHz oscillator, the voltage comparator C1, and output logic represented here as a simple SR latch. The modulator generates a continuous stream of rect- angular, signal-level. It generates the pulses at a fixed frequency, and it modulates or varies their widths in response to variations in the error voltage. The pulses appear at Q, the output of the SR latch. An increase in the error voltage results in a proportional increase in the pulse widths, and, conversely, a decrease in the error voltage results in a proportional decrease in the pulse widths. The oscillator produces a 90 kHz sawtooth that ramps between 1V and 2V. At the beginning of each ramp, the oscillator sets the SR latch sending Q high. As the ramp voltage surpasses the error voltage, C1 resets the SR latch sending Q low. An increase in the error voltage increases the time between the setting and the resetting of the SR latch which , in turn, results in an equal increase in pulse widths: that is, an equal increase in the time Q spends high in each cycle. A decrease in the error voltage has the opposite effect on the pulse widths as it decreases the time between the setting and reset- ting of the SR latch. 4. The power stage: The power stage puts some punch between the output of the modulator by translating the stream of signal-level pulses generated by the modula- tor into a stream of power pulses that swing from ground up to the input voltage while sinking and sourcing as much as 3.5A. The power stage consists of two gate drivers DH and DL, two linear voltage regulators VRegH and VRegL, and two NMOS power FETs Q1 and Q2. The power pulses appear at the SW mode. When Q goes high, DL drives the gate of Q2 low turning Q23 off. While Q2 turns off, the SW potential may remain at just below ground as the body diode of Q2 conducts what was previously reverse current (source-to-drain) in Q2, or the SW potential may swing up to just above the input voltage as the body diode of Q1 conducts what was previously forward current (drain-to-source) in Q2. About 50 ns after Q goes high, DH drives the gate of Q1 high turning Q1 on. If the task remains, Q1 pulls the SW potential up, if not, Q1 simply takes over the conduction responsibility from its own body diode. When Q goes low, the inverse action occurs resulting in the SW poten- tial swinging from the input voltage to the ground. The 50 ns delay between one switch beginning to turn off and the other switch beginning to turn on prevents the switches from ″shooting through″ directly from the input supply to the ground. The PWM circuit drives the pulse stream into the low-pass filter made up of L1 and C OUT. The filter passed the DC component of the stream and attenuates the AC components. The output of the filter is the DC voltage V OUT superimposed with a small ripple voltage. Since the DC component of any periodic waveforms the average value of the waveform, V OUT can be found using: (1) Here T is the switching period in seconds V(t) is the pulse stream. Under DC steady-state conditions, (1) yields (2) Here V IN is the input voltage, and therefore the height of the pulses, in volts, is the width of the pulses in seconds, and D is the ratio of t ON to T, the duty or the duty cycle. The output voltage is programmed using the resistive divider made up for R1 and R2, (3) As Q1 turns on, its source voltage swings up to just below the input voltage. The LM2650 uses a simple technique called ″bootstrapping″ to pull the positive supply rail of DH (at BOOT) up along with the source voltage of Q1, but to a voltage above the input voltage. Because the source of Q1 and the positive supply rail of DH make the same voltage swing together, DH maintains the positive gate-to-source voltage required to turn Q1 on. Q12 plays an active role in pulling the supply rail of DH up and is therefore said to pull itself up by its ″bootstraps″, thus the name of the technique and of the BOOT pin. In the typical application, a capacitor CB is connected out- side the IC between the BOOT and SW pins. When Q2 is on, the input supply charges CB through VRegH and the internal diode D. THE HYSTERETIC CIRCUIT AND LOOP ( Figure 2) Except for C2, the hysteretic circuit borrows all its circuit blocks from the PWM circuit. The hysteretic comparator C2 is a voltage comparator with built-in hysteresis V HYST of typically 30mV centered at 1.25V. www.national.com 7 |
Аналогичный номер детали - LM2650MX-ADJ |
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Аналогичное описание - LM2650MX-ADJ |
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