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KM611001L датащи(PDF) 1 Page - Samsung semiconductor |
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KM611001L датащи(HTML) 1 Page - Samsung semiconductor |
1 / 8 page KM611001/L CMOS SRAM Rev 2.0 July-1996 1 • Fast Access Time 20, 25, 35ns(Max.) • Low Power Dissipation Standby (TTL) : 40 mA(Max.) (CMOS): 2 mA(Max.) 0.5 mA(Max.) - L-ver. Operating KM611001/L -20 : 130 mA(Max.) KM611001/L -25 : 110 mA(Max.) KM611001/L -35 : 100 mA(Max.) • Single 5.0V ± 10% Power Supply • TTL Compatible Inputs and Outputs • Fully Static Operation - No Clock or Refresh required • Three State Outputs • Low Data Retention Voltage : 2V(Min.)- L-Ver Only • Standard Pin Configuration KM611001P/LP : 28-DIP-400 KM611001J/LJ : 28-SOJ-400A The KM611001/L is a 1,048,576-bit high-speed Static Random Access Memory organized as 1,048,576 words by 1 bit. The KM611001/L has separate input and output lines for fast read and write access. The device is fabricated using Samsung`s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high- density high-speed system applications. The KM611001/L is packaged in a 400 mil 28-pin plastic DIP or SOJ. 1M x 1Bit High-Speed CMOS SRAM FEATURES FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION(TOP VIEW) Address Inputs Write Enable Chip Select Data Input Data Output Power (+5V) Ground No Connection Pin Name Pin Function A0-A19 /WE /CS DIN DOUT Vcc Vss N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 SOJ/DIP A0 A1 A2 A3 A4 A5 N.C A6 A7 A8 A9 DOUT /WE Vss Vcc A19 A18 A17 A16 A15 A14 N.C A13 A12 A11 A10 DIN /CS PIN DESCRIPTION GENERAL DESCRIPTION A0 A1 A2 A3 A5 A6 A7 A8 A9 DIN MEMORY ARRAY 512 Rows 2048x1 Columns Pre-Charge Circuit Data Cont. A4 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 /CS /WE I/O Circuit Column Select Clk Gen. Clk Gen. DOUT |
Аналогичный номер детали - KM611001L |
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Аналогичное описание - KM611001L |
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