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MC14072BD датащи(PDF) 1 Page - Motorola, Inc

номер детали MC14072BD
подробное описание детали  B-Suffix Series CMOS Gates
Download  11 Pages
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производитель  MOTOROLA [Motorola, Inc]
домашняя страница  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MC14072BD датащи(HTML) 1 Page - Motorola, Inc

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MOTOROLA CMOS LOGIC DATA
7
MC14001B
B-Suffix Series CMOS Gates
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure (Complemen-
tary MOS). Their primary use is where low power dissipation and/or high
noise immunity is desired.
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range.
• Double Diode Protection on All Inputs Except: Triple Diode Protection
on MC14011B and MC14081B
• Pin–for–Pin Replacements for Corresponding CD4000 Series B Suffix
Devices (Exceptions: MC14068B and MC14078B)
L SUFFIX
CERAMIC
CASE 632
ORDERING INFORMATION
MC14XXXBCP
Plastic
MC14XXXBCL
Ceramic
MC14XXXBD
SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage
– 0.5 to + 18.0
V
Vin, Vout Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
lin, lout
Input or Output Current (DC or Transient),
per Pin
± 10
mA
PD
Power Dissipation, per Package†
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
TL
Lead Temperature (8–Second Soldering)
260
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/
_C From 100_C To 125_C
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
© Motorola, Inc. 1995
REV 3
1/94
MC14001B
Quad 2-Input NOR Gate
MC14002B
Dual 4-Input NOR Gate
MC14011B
Quad 2-Input NAND Gate
MC14012B
Dual 4-Input NAND Gate
MC14023B
Triple 3-Input NAND Gate
MC14025B
Triple 3-Input NOR Gate
MC14068B
8-Input NAND Gate
MC14071B
Quad 2-Input OR Gate
MC14072B
Dual 4-Input OR Gate
MC14073B
Triple 3-Input AND Gate
MC14075B
Triple 3-Input OR Gate
MC14078B
8-Input NOR Gate
MC14081B
Quad 2-Input AND Gate
MC14082B
Dual 4-Input AND Gate


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