AD9163BBCZ datasheet(5/124 Pages) AD

номер детали	AD9163BBCZ

подробное описание детали	DAC update rate up to 12 GSPS

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AD9163

Data Sheet

Rev. 0 | Page 4 of 123

DAC INPUT CLOCK OVERCLOCKING SPECIFICATIONS

VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =

DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.

Maximum guaranteed speed using the temperatures and voltages conditions as shown in Table 2, where VDDx is VDD12_CLK, DVDD,

VDD_1P2, DVDD_1P2, and PLL_LDO_VDD12. Any DAC clock speed over 5.1 GSPS requires a maximum junction temperature of

105°C to avoid damage to the device. See Table 10 for details on maximum junction temperature permitted for certain clock speeds.

Table 2.

Parameter1

Test Conditions/Comments

Min

Typ

Max

Unit

MAXIMUM DAC UPDATE RATE

VDDx = 1.2 V ± 5%

TJMAX = 25°C

6.0

GSPS

TJMAX = 85°C

5.6

GSPS

TJMAX = 105°C

5.4

GSPS

VDDx = 1.2 V ± 2%

TJMAX = 25°C

6.1

GSPS

TJMAX = 85°C

5.8

GSPS

TJMAX = 105°C

5.6

GSPS

VDDx = 1.3 V ± 2%

TJMAX = 25°C

6.4

GSPS

TJMAX = 85°C

6.2

GSPS

TJMAX = 105°C

6.0

GSPS

1

TJMAX is the maximum junction temperature.

POWER SUPPLY DC SPECIFICATIONS

IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted. FIR85 is the finite impulse response with 85 dB digital attenuation.

Table 3.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

8 LANES, 6× INTERPOLATION (80%), 3 GSPS

NCO on, FIR85 on

Analog Supply Currents

VDD25_DAC = 2.5 V

93.8

mA

VDD12A = 1.2 V

3.7

µA

VDD12_CLK = 1.2 V

228.7

mA

VNEG_N1P2 = −1.2 V

−120.7

mA

Digital Supply Currents

DVDD = 1.2 V

598.4

mA

IOVDD = 2.5 V

2.5

mA

SERDES Supply Currents

VDD_1P2 = 1.2 V

Includes VTT_1P2, BIAS_VDD_1P2

443.4

mA

DVDD_1P2 = 1.2 V

72.3

mA

PLL_LDO_VDD12 = 1.2 V

Connected to PLL_CLK_VDD12

81.8

mA

SYNC_VDD_3P3 = 3.3 V

9.4

mA

8 LANES, 8× INTERPOLATION (80%), 5 GSPS

NCO on, FIR85 off (unless otherwise noted)

Analog Supply Currents

VDD25_DAC = 2.5 V

94

100

mA

VDD12A = 1.2 V

80

150

µA

VDD12_CLK = 1.2 V

341

435

mA

VNEG_N1P2 = −1.2 V

−119

−112

mA

Digital Supply Currents

DVDD = 1.2 V

NCO on, FIR85 off

495

878

mA

IOVDD = 2.5 V

2.5

2.7

mA

SERDES Supply Currents

VDD_1P2 = 1.2 V

Includes VTT_1P2, BIAS_VDD_1P2

477

681

mA

DVDD_1P2 = 1.2 V

89

130

mA

PLL_LDO_VDD12 = 1.2 V

Connected to PLL_CLK_VDD12

81

112

mA

SYNC_VDD_3P3 = 3.3 V

9.3

11

mA

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