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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9164BBCARL датащи(PDF) 10 Page - Analog Devices |
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AD9164BBCARL датащи(HTML) 10 Page - Analog Devices |
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10 / 137 page  Data Sheet AD9164 Rev. A | Page 9 of 136 DIGITAL INPUT DATA TIMING SPECIFICATIONS VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 = DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted. Table 7. Parameter Test Conditions/Comments Min Typ Max Unit LATENCY1 Interface 1 PCLK2 cycle Interpolation See Table 33 Power-Up Time From DAC output off to enabled 10 ns DETERMINISTIC LATENCY Fixed 12 PCLK2 cycles Variable 2 PCLK2 cycles SYSREF± TO LOCAL MULTIFRAME CLOCKS (LMFC) DELAY 4 DAC clock cycles 1 Total latency (or pipeline delay) through the device is calculated as follows: Total Latency = Interface Latency + Fixed Latency + Variable Latency + Pipeline Delay See Table 33 for examples of the pipeline delay per block. 2 PCLK is the internal processing clock for the AD9164 and equals the lane rate ÷ 40. JESD204B INTERFACE ELECTRICAL SPECIFICATIONS VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 = DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted. VTT is the termination voltage. Table 8. Parameter Symbol Test Conditions/Comments Min Typ Max Unit JESD204B DATA INPUTS Input Leakage Current TA = 25°C Logic High Input level = 1.2 V ± 0.25 V, VTT = 1.2 V 10 µA Logic Low Input level = 0 V −4 µA Unit Interval UI 80 1333 ps Common-Mode Voltage VRCM AC-coupled, VTT = VDD_1P21 −0.05 +1.85 V Differential Voltage R_VDIFF 110 1050 mV VTT Source Impedance ZTT At dc 30 Ω Differential Impedance ZRDIFF At dc 80 100 120 Ω Differential Return Loss RLRDIF 8 dB Common-Mode Return Loss RLRCM 6 dB SYSREF± INPUT Differential Impedance 165-ball CSP_BGA 110 Ω 169-ball CSP_BGA 121 Ω DIFFERENTIAL OUTPUTS (SYNCOUT±)2 Driving 100 Ω differential load Output Differential Voltage VOD 350 420 450 mV Output Offset Voltage VOS 1.15 1.2 1.27 V 1 As measured on the input side of the ac coupling capacitor. 2 IEEE Standard 1596.3 LVDS compatible. |
Аналогичный номер детали - AD9164BBCARL |
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Аналогичное описание - AD9164BBCARL |
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