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AD5592RBCBZ-1-RL7 датащи(PDF) 7 Page - Analog Devices

номер детали AD5592RBCBZ-1-RL7
подробное описание детали  Control and monitoring
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD5592RBCBZ-1-RL7 датащи(HTML) 7 Page - Analog Devices

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Data Sheet
AD5592R
Rev. C | Page 7 of 42
Parameter
Min
Typ
Max
Unit1
Test Conditions/Comments
VDD = 3 V (Normal Mode)
1.1
mA
I/O0 to I/O7 are DACs, internal reference,
gain = 1
1
mA
I/O0 to I/O7 are DACs, external reference,
gain = 1
1.1
mA
I/O0 to I/O7 are DACs and sampled by the
ADC, internal reference, gain = 1
0.78
mA
I/O0 to I/O7 are DACs and sampled by the
ADC, external reference, gain = 1
0.75
mA
I/O0 to I/O7 are ADCs, internal reference,
gain = 1
0.5
mA
I/O0 to I/O7 are ADCs, external reference,
gain = 1
0.45
mA
I/O0 to I/O7 are general-purpose outputs
0.45
mA
I/O0 to I/O7 are general-purpose inputs
VLOGIC
1.8
VDD
V
AD5592R-1 only
ILOGIC
3
µA
AD5592R-1 only
1
All specifications expressed in decibels are referred to full-scale input (FSR) and tested with an input signal at 0.5 dB below full scale, unless otherwise noted.
2
Guaranteed by design and characterization; not production tested.
3
DC specifications tested with the outputs unloaded, unless otherwise noted. Linearity calculated using a code range of 8 to 4095. There is an upper dead band of
10 mV when VREF = VDD.
4
When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 33).
TIMING CHARACTERISTICS
Guaranteed by design and characterization, not production tested; all input signals are specified with tR = tF = 5 ns (10% to 90% of VDD)
and timed from a voltage level of (VIL + VIH)/2; TA = TMIN to TMAX, unless otherwise noted.
Table 3. AD5592R Timing Characteristics
Parameter
2.7 V ≤ VDD < 3 V
3 V ≤ VDD ≤ 5.5 V
Unit
Test Conditions/Comments
t1
33
20
ns min
SCLK cycle time, write operation
50
50
ns min
SCLK cycle time, read operation
t2
16
10
ns min
SCLK high time
t3
16
10
ns min
SCLK low time
t4
15
10
ns min
SYNC falling edge to SCLK falling edge setup time
2
2
µs max
SYNC falling edge to SCLK falling edge setup time1
t5
7
7
ns min
Data setup time
t6
5
5
ns min
Data hold time
t7
15
10
ns min
SCLK falling edge to SYNC rising edge
t8
30
30
ns min
Minimum SYNC high time for register write operations
60
60
ns min
Minimum SYNC high time for register read operations
t9
0
0
ns min
SYNC rising edge to next SCLK falling edge
t10
25
25
ns max
SCLK rising edge to SDO valid
t11
250
250
ns min
RESET low pulse width (not shown in Figure 4)
1
When reading an ADC conversion.


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