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AD5593RBCPZ-RL7 датащи(PDF) 10 Page - Analog Devices |
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AD5593RBCPZ-RL7 датащи(HTML) 10 Page - Analog Devices |
10 / 34 page Data Sheet AD5593R Rev. B | Page 9 of 33 GND I/O7 I/O6 I/O5 VDD I/O1 I/O0 I/O2 12 11 10 1 3 4 9 2 AD5593R TOP VIEW (Not to Scale) Figure 4. 16-Lead LFCSP Pin Configuration Table 7. 16-Ball LFCSP Pin Function Descriptions Pin No. Mnemonic Description 1 VDD Power Supply Input. The AD5593R operates from 2.7 V to 5.5 V. Decouple the supply with a 0.1 μF capacitor to GND. 2 to 5, 8 to 11 I/O0 to I/O7 Input/Output 0 through Input/Output 7. These pins can be independently configured as DACs, ADCs, or general- purpose digital inputs or outputs. The function of each pin is determined by programming the appropriate bits in the configuration registers. 6 VREF Reference Input/Output. When the internal reference is enabled, the 2.5 V reference voltage is available on the pin. A 0.1 μF capacitor connected from the VREF pin to GND is recommended to achieve the specified performance from the AD5593R. When the internal reference is disabled, an external reference must be applied to this pin. The voltage range for the external reference is 1 V to VDD. 7 VLOGIC Interface Power Supply. The voltage ranges from 1.8 V to 5.5 V. 12 GND Ground Reference Point for All Circuitry. 13 SDA Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the input shift register. SDA is a bidirectional, open-drain line that must be pulled to the VLOGIC supply with an external pull-up resistor. 14 SCL Serial Clock Line. This is pin used in conjunction with the SDA line to clock data into or out of the 16-bit input register. 15 RESET Asynchronous Reset Pin. Tie this pin high for normal operation. When this pin is brought low, the AD5593R is reset to its default configuration. 16 A0 Address Input. This pin sets the LSB of the 7-bit slave address. |
Аналогичный номер детали - AD5593RBCPZ-RL7 |
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Аналогичное описание - AD5593RBCPZ-RL7 |
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