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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD5675BRUZ-REEL7 датащи(PDF) 6 Page - Analog Devices |
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AD5675BRUZ-REEL7 датащи(HTML) 6 Page - Analog Devices |
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6 / 27 page  Data Sheet AD5675 Rev. B | Page 5 of 26 AC CHARACTERISTICS VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, 1.8 V ≤ VLOGIC ≤ 5.5 V, all specifications TA = −40°C to +125°C, unless otherwise noted. Guaranteed by design and characterization; not production tested. Table 3. Parameter Min Typ Max Unit Test Conditions/Comments Output Voltage Settling Time 1 5 8 µs ¼ to ¾ scale settling to ±2 LSB Slew Rate 0.8 V/µs Digital-to-Analog Glitch Impulse1 1.4 nV-sec 1 LSB change around major carry (gain = 1) Digital Feedthrough1 0.13 nV-sec Digital Crosstalk1 0.1 nV-sec Analog Crosstalk1 −0.25 nV-sec Gain = 1 −1.3 nV-sec Gain = 2 DAC-to-DAC Crosstalk1 −2.0 nV-sec Gain = 2 Total Harmonic Distortion (THD)1, 2 −80 dB TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz Output Noise Spectral Density (NSD)1 80 nV/√Hz DAC code = midscale, bandwidth = 10 kHz, gain = 1 and 2 Output Noise 6 µV p-p 0.1 Hz to 10 Hz, gain = 1 Signal-to-Noise Ratio (SNR) 90 dB TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz Spurious-Free Dynamic Range (SFDR) 83 dB TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz Signal-to-Noise-and-Distortion Ratio (SINAD) 80 dB TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz 1 See the Terminology section. 2 Digitally generated sine wave at 1 kHz. TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, all specifications −40°C to +125°C, unless otherwise noted. Table 4. Parameter1, 2 Min Max Unit Description t1 0.92 µs SCL cycle time t2 0.11 µs tHIGH, SCL high time t3 0.44 µs tLOW, SCL low time t4 0.04 µs tHD,STA, start/repeated start hold time t5 40 ns tSU,DAT, data setup time t6 3 −0.04 µs tHD,DAT, data hold time t7 −0.045 µs tSU,STA, repeated start setup time t8 0.195 µs tSU,STO, stop condition setup time t9 0.12 µs tBUF, bus free time between a stop condition and a start condition t10 4 0 ns tR, rise time of SCL and SDA when receiving t114, 5 20 + 0.1 CB ns tF, fall time of SCL and SDA when transmitting/receiving t12 20 ns LDAC pulse width t13 0.4 ns SCL rising edge to LDAC rising edge t14 4.8 ns RESET minimum pulse width low, 1.8 V ≤ VLOGIC ≤ 2.7 V 6.2 ns RESET minimum pulse width low, 2.7 V ≤ VLOGIC ≤ 5.5 V t15 132 ns RESET activation time, 1.8 V ≤ VLOGIC ≤ 2.7 V 80 ns RESET activation time, 2.7 V ≤ VLOGIC ≤ 5.5 V tSP 6 0 ns Pulse width of suppressed spike CB5 400 pF Capacitive load for each bus line 1 See Figure 2 and Figure 3. 2 Guaranteed by design and characterization; not production tested. 3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the minimum VIH of the SCL signal) to bridge the undefined region of the SCL falling edge. 4 tR and tF are measured from 0.3 × VDD to 0.7 × VDD. 5 CB is the total capacitance of one bus line in picofarads. 6 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns. |
Аналогичный номер детали - AD5675BRUZ-REEL7 |
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Аналогичное описание - AD5675BRUZ-REEL7 |
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