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AD5676R датащи(PDF) 8 Page - Analog Devices |
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AD5676R датащи(HTML) 8 Page - Analog Devices |
8 / 28 page Data Sheet AD5676 Rev. B | Page 7 of 27 DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4. VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, VREF = 2.5 V, all specifications −40°C to +125°C, unless otherwise noted. Table 5. 1.8 V ≤ VLOGIC < 2.7 V 2.7 V ≤ VLOGIC ≤ 5.5 V Parameter1 Symbol Min Max Min Max Unit SCLK Cycle Time t1 120 83.3 ns SCLK High Time t2 33 25.3 ns SCLK Low Time t3 2.8 3.25 ns SYNC to SCLK Falling Edge t4 75 50 ns Data Setup Time t5 1.2 0.5 ns Data Hold Time t6 0.3 0.4 ns SCLK Falling Edge to SYNC Rising Edge t7 16.2 13 ns Minimum SYNC High Time t8 55.1 45 ns SDO Data Valid from SCLK Rising Edge t10 21.5 22.7 ns SCLK Falling Edge to SYNC Rising Edge t11 24.4 20.3 ns SYNC Rising Edge to SCLK Rising Edge t12 85.5 54 ns 1 Maximum SCLK frequency is 25 MHz or 15 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested. Circuit Diagram and Daisy-Chain and Readback Timing Diagrams 200µA IOL 200µA IOH VOH (MIN) TO OUTPUT PIN 20pF CL Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications t4 t5 t6 t8 SDO SDI SYNC SCLK 48 24 DB23 DB0 DB23 DB0 DB23 INPUT WORD FOR DAC N UNDEFINED INPUT WORD FOR DAC N + 1 INPUT WORD FOR DAC N DB0 t11 t12 t10 Figure 4. Daisy-Chain Timing Diagram |
Аналогичный номер детали - AD5676R |
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Аналогичное описание - AD5676R |
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