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AD7984 датащи(PDF) 5 Page - Analog Devices

номер детали AD7984
подробное описание детали  Devices Connected
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Circuit Note
CN-0269
Rev. 0 | Page 5 of 12
Settling Time Analysis
When the circuit shown in Figure 1 is operating in the
continuous switching mode, all the 16-channel signal-ended or
8-channel differential signal streams are merged into a time-
division multiplexed signal by the two stage multiplexer, the
ADG5208 and ADG5236. The signal is then buffered by the
AD8065 that has a high impedance, low capacitance input.
Then the low impedance output of AD8065 buffer drives the
AD8475 stage that attenuates, level shifts, and performs the
single-ended to differential conversion. An RC (10 Ω, 2.2 nF)
filter is placed at the input of the AD7984 ADC in order to limit
out-of-band noise and attenuate the kickback from the switched
capacitor input of the ADC. The −3 dB bandwidth of the filter
is 7.2 MHz. (See Front-End Amplifier and RC Filter Design for a
Precision SAR Analog-to-Digital Converters, Analog Dialogue
46-12, December 2012).
For the purposes of calculating settling time, the circuit can be
divided into four parts as shown in Figure 5.
Figure 5. Sub-Stage Block Diagram for Settling Time Analysis
Then the total settling time is estimated to be the root sum
square (rss) of settling time of each stage
2
_
2
_
2
_
2
_
_
RC
S
ATN
S
BUF
S
MUX
S
ALL
S
t
t
t
t
t
+
+
+
=
In order to settle to within a specific error band at a sampling
rate, fS , the relationship below must be satisfied.
tS_ALL + tDD + tMD < 1/fS
Or, fS <1/(tS_ALL + tDD + tMD)
Settling Time for the Multiplexer Stage
The equivalent circuit for a CMOS switch can be approximated
as an ideal switch in series with a resistor (RON) and in parallel
with two capacitors (CS, CD). The multiplexer stage and
associated filters can therefore be modeled as shown in Figure 6.
Figure 6. First-Order Model for Input Pre-Filter, Multiplexer, and AD8065 Input
Note that the ADG5236 model does not show the series switch
because it only switches when changing from single-ended to
differential mode inputs.
The pre-filter in front of multiplexer is not shown in Figure 1.
This pre-filter is used for noise suppression. Also, the RP resistor
combined with protection diodes and the TVS provides
additional transient and over-voltage protection for hostile
environments. The protection components are shown in the
complete circuit schematic contained in the CN-0269 Design
Support Package.
The RS is the 1 kΩ resistor in series with non-inverting input of
the AD8065, and CIN is the input capacitance of AD8065. The
input impedance of AD8065 is 1 GΩ||2.2 pF, and the 1 GΩ
resistance can be ignored.
The circuit in Figure 6 was simulated using NI Multisim™ as
shown in Figure 7, with the following component values:
Pre-filter: RP = 300 Ω; CP = 120 pF;
ADG5208: RON =160 Ω; CS = 5.5 pF; CD = 52 pF;
ADG5236: RON =160 Ω; CS = 2.5 pF; CD = 12 pF;
AD8065: RS =1 kΩ; CIN = 2.2 pF;
Figure 7. NI Multisim Simulation Circuit for the Pre-Filter, Multiplexer, and AD8065 Input
PART 3
ATTENUATION
AD8475
PART 1
tS_MUX
tS_BUF
tS_ATN
MUX
ADG5208
ADG5236
PART 4
RC + ADC
AD7984
tS_RC
PART 2
BUFFER
AD8065
D
CS
CS
CD
VSS
CS
VSS
VSS
CD
VSS
VSS
VSS
VSS
VSS
SW1
SW2
RP
RP
ADG5208
ADG5236
RON
RON
RON
CP
CP
AI 1
AI 2
PRE-FILTER
RS
CIN
AD8065
SW1
SW2
RP1
300Ω
RP2
300Ω
CP1
120pF
CD1
52pF
RON3
160Ω
CD2
15pF
V1
259kHz
4V
RS
1kΩ
CIN
2.2pF
CA1
10pF
CS1
5.5pF
CS2
5.5pF
ADG5208
CS3
2.5pF
ADG5236
S1
10V
S2
–10V
RON1
160Ω
RON2
160Ω
FIRST
RC
SECOND
RC
THIRD
RC
FOURTH
RC
XSC1
A
B C
D
G
T
CP2
120pF
CA2
10pF


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