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AD7984 датащи(PDF) 2 Page - Analog Devices |
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AD7984 датащи(HTML) 2 Page - Analog Devices |
2 / 12 page CN-0269 Circuit Note Rev. 0 | Page 2 of 12 This circuit is an ideal solution for a multichannel data acquisition card for many industrial applications including process control, and power line monitoring. CIRCUIT DESCRIPTION The circuit shown in Figure 1 is a classic multichannel non- synchronous data acquisition signal chain consisting of a multiplexer, amplifiers, and an ADC. The architecture allows fast sampling of multiple channels using a single ADC, providing low cost and excellent channel-to- channel matching. Channel-to-channel switching speed is limited by the settling time of the various components following the multiplexer in the signal chain, because the multiplexer can present a full-scale step voltage output to the downstream amplifier and ADC. The components in this circuit have been specifically chosen to minimize the settling time and maximize channel-to-channel switching speed. Component Selection The ADG5208 multiplexer switches one of eight inputs to a common output, as determined by the 3-bit binary address lines. The ADG5236 contains two independently selectable single-pole/double throw (SPDT) switches. Two ADG5208 switches, combined with one ADG5236, allow 16 single-ended channels or 8 true differential channels to be connected to the rest of the signal chain using a 4-bit digital control signal. The 4-bit digital signal is generated by a 4-bit binary up/down counter triggered by the same signal used for the convert (CNV) input to the 18-bit, 1.33 MSPS AD7984 ADC. The AD8065 JFET input op amp has a 145 MHz bandwidth and is configured as a unity-gain buffer to provide excellent settling time performance and extremely high input impedance. The AD8065 also provides very low impedance output to drive the AD8475 funnel amp attenuation stage. The advantages of fully differential signal chain are good common-mode rejection and reduction in second-order distortion products. In order to process ±10 V industrial level signals by modern low voltage differential input ADCs, the attenuation and level shifting stage is necessary. The AD8475, fully differential, attenuating (funnel) amplifier with integrated precision gain resistors provides precision attenuation (by 0.4× or 0.8×), common-mode level shifting, and single- ended-to-differential conversion along with input overvoltage protection. Fast settling time (50 ns to 0.001%), and low noise performance (10 nV/√Hz) make the AD8475 well suited to drive 18-bit differential input ADCs at sampling rates up to 4 MSPS. The AD7984, 18-bit, PulSAR® ADC selected in this circuit provides 18-bit resolution at 1.33 MSPS when sampling a single channel. However, the settling time of various components in the signal chain limit the overall accuracy when sequentially switching between channels. For example, 16-bit performance is achieved when switching between channels at a 250 kHz rate. Timing Analysis When the circuit shown in Figure 1 is operating in the continuous switching mode, all the 16-channel signal-ended or 8-channel differential signal streams are merged into a time-division multiplexed signal by the two stage multiplexer comprised of the ADG5208 and the ADG5236. The multiplexed signal drives the buffer circuit (AD8065) and the attenuation and level shift circuit (AD8475). The output signal of the AD8475 drives the differential input ADC through an RC filter (2.2 nF, 10 Ω). The multiplexed input signal typically consists of large voltage steps when switching between channels. In the worst case, one channel is at negative full scale, while the next channel is at positive full scale. Therefore, the step can be as large as the full range of input signal, in this case, 20 V. It is a tremendous challenge for the analog signal chain to settle to high precision from such a large step signal level in a short time. The timing of the circuit must be carefully examined to determine the amount of settling time available at various sampling rates and the settling time required by the circuits in the signal chain. Figure 2 shows the basic timing diagram of the system, and this is where the analysis starts. Figure 2. Multichannel Data Acquisition Circuit Timing ACQUISITION [0000] [0001] SETTLING TO CH0 SETTLING TO CH1 CONVERSION tCONV tACQ ACQUISITION tS tMD tDD tSETTLE CNV STATUS [CH3 TO CH0] VOUT_SW |
Аналогичный номер детали - AD7984 |
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Аналогичное описание - AD7984 |
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