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AD7984 датащи(PDF) 3 Page - Analog Devices

номер детали AD7984
подробное описание детали  Devices Connected
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производитель  AD [Analog Devices]
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Circuit Note
CN-0269
Rev. 0 | Page 3 of 12
Digital Delay
In the circuit shown in Figure 1, the ADC and multiplexer are
both triggered by the rising edge of CNV signal from digital
controller. At this point, the SAR ADC has completed the
acquisition of the sample and starts the conversion cycle.
Ideally, the signal chain has one full sampling period to settle to
the next channel, but there are delays in the digital circuits that
decrease the available settling time. In Figure 2, tDD is the sum of
the delay through the NAND gate and the counter CLK-to-
OUT delay. This digital delay can be found from the data sheet
of each component, and is approximately 8 ns total.
The time shown as tMD in Figure 2 is the delay through the two
stage multiplexer measured from the 50% point of the digital
input to the point that the analog output signal starts to settle.
Since the ADG5208 and ADG5236 are switched simultaneously
in this circuit, the tMD marked in Figure 2 is equal to the delay
generated by the slower one, which is the ADG5208.
The transition time delay of multiplexer is easy to find in the
data sheet. However, the transition delay on the data sheet is the
delay time between the 50% of the digital input and the 90%
point of the digital output as shown in Figure 3.
So tMD is calculated using the equation:
tMD = tTRANSITION − tSETTLE (90%)
(1)
The maximum settling time left for analog signal chain at a
sampling rate of
��������canbeestimatedbytheequation:
tSETTLE(fs) = 1/fS – tDD − tMD
(2)
A good first order approximation for estimating multiplexer
settling time is to treat the multiplexer in the on state as a
simple RC circuit with time constant of RON × CD.
The time for switch to settle to within a % error can be
calculated by the equation below. See the AN-1024 Application
Note, “How to Calculate the Settling Time and Sampling Rate of
a Multiplexer” for more details.
The test circuit for measuring the transition delay with a load of
300 Ω||35 pF is shown in Figure 3. Under this test configuration,
the settling time can be estimated by Equation 3.
(
)
L
D
L
ON
L
ON
SETTLE
C
C
R
R
R
R
error
t
+
+


=
100
%
ln
(3)
Figure 3. ADG5208 Transition Delay Test Circuit
3V
0V
OUTPUT
ADDRESS
DRIVE (VIN)
tTRANSITION
tTRANSITION
50%
50%
90%
90%
OUTPUT
ADG5208
A0
A1
A2
50
300Ω
GND
S1
S2 TO S7
S8
D
35pF
VIN
2.0V
EN
VDD
VSS
VSS
VDD
VS1
VS8
tMD
tr < 20ns
tf < 20ns


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