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AD5530BRU датащи(PDF) 10 Page - Analog Devices

номер детали AD5530BRU
подробное описание детали  Serial Input, Voltage Output 12-/14-Bit DACs
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REV. 0
–10–
AD5530/AD5531
2V/DIV
2V/DIV
PD
VOUT
VDD = +15V
VSS = –15V
REFIN = +5V
REFAGND = 0V
TA = +25 C
TPC 13. Typical Power-Down Time
GENERAL DESCRIPTION
DAC Architecture
The AD5530/AD5531 are pin-compatible 12-/14-bit DACs.
The AD5530 consists of a straight 12-bit R-2R voltage mode DAC,
while the AD5531 consists of a 14-bit R-2R section. Using a +5 V
reference connected to the REFIN pin and REFAGND tied to
0 V, a bipolar
±10 V voltage output results. The DAC coding is
straight binary.
Serial Interface
Serial data on the SDIN input is loaded to the input register under
the control of SCLK,
SYNC, and LDAC. A write operation
transfers a 16-bit word to the AD5530/AD5531. Figures 1 and 2
show the timing diagrams. Figure 3 shows the contents of the
input shift register. Twelve or 14 bits of the serial word are data
bits; the rest are don’t cares.
X X D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1 D0 X X
DATA BITS
DB15 (MSB)
DB0 (LSB)
Figure 3a. AD5530 Input Shift Register Contents
X X D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA BITS
DB15 (MSB)
DB0 (LSB)
Figure 3b. AD5531 Input Shift Register Contents
The serial word is framed by the signal,
SYNC. After a high to low
transition on
SYNC, data is latched into the input shift register
on the falling edges of SCLK. There are two ways in which the
DAC register and output may be updated. The
LDAC signal is
examined on the falling edge of
SYNC; depending on its status,
either a synchronous or asynchronous update is selected. If
LDAC is low, then the DAC register and output are updated on
the low to high transition of
SYNC. Alternatively, if LDAC is
high upon sampling, the DAC register is not loaded with the
new data on a rising edge of
SYNC. The contents of the DAC
register and the output voltage will be updated by bringing
LDAC low any time after the 16-bit data transfer is complete.
LDAC may be tied permanently low if required. A simplified
diagram of the input loading circuitry is illustrated in Figure 4.
LDAC
12-/14-BIT DAC
DAC REGISTER
SYNC REGISTER
16-BIT SHIFT
REGISTER
SYNC
SDIN
REFIN
14
14
14
OUTPUT
SDO
Figure 4. Simplified Serial Interface
Data written to the part via SDIN is available on the SDO pin
16 clocks later if the readback function is not used. SDO data is
clocked out on the falling edge of the serial clock with some delay.
PD Function
The
PD pin allows the user to place the device into power-down
mode. While in this mode, power consumption is at a minimum;
the device draws only 50
µA of current. The PD function does
not affect the contents of the DAC register.
READBACK Function
The AD5530/AD5531 allows the data contained in the DAC
register to be read back if required. The pins involved are the
RBEN and SDO (serial data out). When RBEN is taken low, on
the next falling edge of SCLK, the contents of the DAC register
are transferred to the shift register.
RBEN may be used to frame
the readback data by leaving it low for 16 clock cycles, or it may
be asserted high after the required hold time. The shift register
contains the DAC register data and this is shifted out on the
SDO line on each falling edge of SCLK with some delay. This
ensures the data on the serial data output pin is valid for the
falling edge of the receiving part. The two MSBs of the 16-bit
word will be ‘0’s.
CLR Function
The falling edge of
CLR causes V
OUT to be reset to the same
potential as DUTGND. The contents of the registers remain
unchanged, so the user can reload the previous data with
LDAC
after
CLR is asserted high. Alternatively, if LDAC is tied low,
the output will be loaded with the contents of the DAC register
automatically after
CLR is brought high.
Output Voltage
The DAC transfer function is as follows:
V
REFIN
REFAGND
D
E AGND
REFIN
DUTGND
OUT
N
×
+ ×


22
2
2
[
] –
RF
where:
D is the decimal data word loaded to the DAC register,
N is the resolution of the DAC.
Bipolar Configuration
Figure 5 shows the AD5530/AD5531 in a bipolar circuit configu-
ration. REFIN is driven by the AD586, 5 V reference, while the
REFAGND and DUTGND pins are tied to GND. This results
in a bipolar output voltage ranging from –10 V to +10 V. Resistor
R1 is provided (if required) for gain adjust. Figure 6 shows the
transfer function of the DAC when REFAGND is tied to 0 V.


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