CDCF2510

3.3V PHASELOCK LOOP CLOCK DRIVER

SCAS628D − APRIL 1999 − REVISED DECEMBER 2004

6

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

LOAD CIRCUIT FOR OUTPUTS

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

tpd

50% VCC

3 V

0 V

VOH

VOL

Input

0.4 V

2 V

tr

tf

0.4 V

2 V

Output

500

W

50% VCC

25 pF

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR

≤ 133 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf ≤ 1.2 ns.

C. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

tsk(o)

tsk(o)

tphase error

CLKIN

FBIN

Any Y

Any Y

Any Y

FBOUT

Figure 2. Phase Error and Skew Calculations