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CS7250B датащи(PDF) 7 Page - Cirrus Logic |
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CS7250B датащи(HTML) 7 Page - Cirrus Logic |
7 / 11 page 7 DS1072PP1 CS7250B 3 Characteristics and Specifications Table 3-5. Audio Interface Timing The following timing information is valid across the full range of recommended operating conditions. Parameter 1 1.Digital microphone interface timing. Symbol Min Typ Max Units CLK cycle time tCY 313 — 3333 ns CLK duty cycle — 60:40 — 40:60 — CLK rise/fall time — — — 6 ns DATA enable time From rising CLK edge, LRSEL = 0 From falling CLK edge, LRSEL = 1 tR_EN tL_EN 14 14 — — — — ns ns DATA valid time From rising CLK edge, LRSEL = 0 From falling CLK edge, LRSEL = 1 tR_DV tL_DV 20 20 — — 90 90 ns ns DATA disable time From falling CLK edge, LRSEL = 0 From rising CLK edge, LRSEL = 1 tR_DIS tL_DIS — — — — 10 10 ns ns Notes: • The DATA output is high-impedance when not outputting data; this enables the outputs of two microphones to be connected together with the data from one microphone interleaved with the data from the other. (The microphones must be configured to transmit on opposite channels in this case.) • In a typical configuration, the left channel is transmitted following the rising CLK edge (LRSEL = 1). In this case, the left channel should be sampled by the receiving device on the falling CLK edge. • Similarly, the right channel is typically transmitted following the falling CLK edge (LRSEL = 0). In this case, the right channel should be sampled by the receiving device on the rising CLK edge. • The CS7250B operating mode is selected according to the CLK frequency; see Table 3-4 for further details. tL_EN CLK (input) tL_DIS tR_EN tR_DIS tCY DATA is high-impedance (Hi-Z) when not outputting data DATA (LRSEL = 1) DATA (LRSEL = 0) tR_DV tL_DV |
Аналогичный номер детали - CS7250B |
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Аналогичное описание - CS7250B |
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