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DAC600 датащи(PDF) 2 Page - Burr-Brown (TI) |
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DAC600 датащи(HTML) 2 Page - Burr-Brown (TI) |
2 / 12 page ® DAC600 2 T Same as specification for DAC600AN. NOTES: (1) Linearity tests are measured into a virtual ground (op amp). (2) Gain error in % is calculated by: GE (%) = (3) Settling time is influenced by the load due to fast edge speeds. Use good transmission line techniques for best results. (4) Spurious free dynamic range is measured from the fundamental frequency to any harmonic or non-harmonic spurs within the bandwidth fCLK/2C, unless otherwise specified. SPECIFICATIONS ELECTRICAL At +25 °C V REF = +1.0V, VEEA = VEED = –5.2V, unless otherwise noted. DAC600AN DAC600BN PARAMETER CONDITIONS TEMP MIN TYP MAX MIN TYP MAX UNITS DIGITAL INPUTS Logic 12 Parallel Input Lines, ECL Resolution 12 T Bits ECL Logic Input Levels: VIL Logic “0” Full –1.48 –1.95 –2 TT T V IIL Full 2 T µA VIH Logic “1” Full –1.1 –0.75 0 TT T V IIH Full 200 T µA DIGITAL TIMING Input Data Rate Full DC 256 TT MHz CLK Pulse Width High or Low Full 1.95 T ns Set-up Time Full 1.5 1.0 TT ns Hold Time (Referred to CLK) Full 1.9 1.7 TT ns Propagation Delay Full 2 T ns ANALOG OUTPUT Bipolar Output Current RL = 0Ω Full 19 20 21 TT T mA Output Resistance Full 47.5 50 52.5 49 T 51 Ω Output Capacitance Full 15 T pF CONTROL AMPLIFIER Input Resistance Full 800 T Ω Full Power Bandwidth –3dB Full 10 T MHz Offset +25 °C0 ±10 ±0.5 mV Input Reference Range Full 100mV ±1.25 TT V TRANSFER CHARACTERISTICS Integral Linearity Error(1): VOUT NOT Best Fit Straight Line +25 °C ±0.012 ±0.024 ±0.006 ±0.012 %FSR VOUT NOT Full ±0.024 ±0.036 ±0.012 ±0.024 %FSR VOUT +25 °C ±0.1 ±0.1 %FSR Differential Linearity Error(1): VOUT NOT +25 °C ±0.024 ±0.012 %FSR VOUT NOT Full ±0.036 ±0.024 %FSR VOUT +25 °C ±0.1% ±0.1% %FSR 12-Bit Monotonicity +25 °C Guaranteed Guaranteed Full Typical Guaranteed Output Offset Current: VOUT NOT Bits 1-12 HIGH +25 °C 75 150 50 100 µA VOUT NOT Full 57 150 50 100 µA Gain Error(2) +25 °C ±0.5 ±1.5 ±0.5 ±1.0 % Full ±1.3 ±2.0 ±1.1 ±2.0 % Output Leakage Current VREF = 0V, Bits 1-12 LOW, VOUT NOT +25 °C10 75 5 50 µA TIME DOMAIN PERFORMANCE Glitch Energy Major Carry +25 °C 5.6 T pVs Fall Time 90% to 10% +25 °C 510 T ps Rise Time 10% to 90% +25 °C 770 T ps Settling Time(3) ±0.1% FSR Major Carry, 1 LSB Change Full 4 T ns ±0.024% FSR Full 15 T ns DYNAMIC PERFORMANCE Spurious Free Dynamic Range (4) fO = 1MHz fCLOCK = 50MHz +25 °C 74 70 77 dBFS(3) fO = 10MHz fCLOCK = 50MHz +25 °C 71 64 73 dBFS fO = 1MHz fCLOCK = 100MHz +25 °C 72 70 75 dBFS fO = 10MHz fCLOCK = 100MHz +25 °C 68 66 70 dBFS fO = 20MHz fCLOCK = 100MHz +25 °C 61 58 62 dBFS fO = 10MHz fCLOCK = 200MHz +25 °C 66 66 70 dBFS fO = 20MHz fCLOCK = 200MHz +25 °C 58 62 67 dBFS fO = 50MHz fCLOCK = 200MHz +25 °C 52 50 55 dBFS Output Noise Bits 1-12 HIGH +25 °C 10.6 T nV/ √Hz POWER SUPPLIES Supply Voltages: VEE Full –4.5 –5.2 –5.5 TT T V Supply Currents: IEEA Pins 33 and 34 Full 30 46 60 TT T mA IEED Pins 5 and 55 Full 110 150 190 TT T mA Power Consumption Operating Full 900mW 1.3 TT W TEMPERATURE RANGE Specification: DAC600AN, BN Ambient Full –40 +85 TT °C θ JA 30 T °C/W VMEASURED (FS) –VIDEAL (FS) X 100 VIDEAL (FS) |
Аналогичный номер детали - DAC600 |
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Аналогичное описание - DAC600 |
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