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GS8180QV36BD-200 датащи(PDF) 1 Page - GSI Technology

номер детали GS8180QV36BD-200
подробное описание детали  18Mb Burst of 2 SigmaQuad SRAM
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производитель  GSI [GSI Technology]
домашняя страница  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS8180QV36BD-200 датащи(HTML) 1 Page - GSI Technology

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Rev: 1.02b 11/2011
1/28
© 2007, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180QV18/36BD-200/167
18Mb Burst of 2
SigmaQuad SRAM
200 MHz–167 MHz
2.5 V VDD
1.8 V or 1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual DoubleData Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• 2.5 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
• RoHS-compliant 165-bump, 13 mm x 15 mm, 1 mm bump
pitch BGA package
SigmaRAM™ Family Overview
GS8180QV18/36B are built in compliance with the
SigmaQuad SRAM pinout standard for Separate I/O
synchronous SRAMs. They are18,874,368-bit (18Mb)
SRAMs. These are the first in a family of wide, very low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
SigmaQuad SRAMs are offered in a number of configurations.
Some emulate and enhance other synchronous separate I/O
SRAMs. A higher performance SDR (Single Data Rate) Burst
of 2 version is also offered. The logical differences between
the protocols employed by these RAMs hinge mainly on
various combinations of address bursting, output data
registering, and write cueing. Along with the Common I/O
family of SigmaRAMs, the SigmaQuad family of SRAMs
allows a user to implement the interface protocol best suited to
the task at hand.
Clocking and Addressing Schemes
A Burst of 2 SigmaQuad SRAM is a synchronous device. It
employs two input register clock inputs, K and K. K and K are
independent single-ended clock inputs, not differential inputs
to a single differential clock input buffer. The device also
allows the user to manipulate the output register clock inputs
quasi independently with the C and C clock inputs. C and C are
also independent single-ended clock inputs, not differential
inputs. If the C clocks are tied high, the K clocks are routed
internally to fire the output registers instead.
Each internal read and write operation in a SigmaQuad-II B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore the address field of a
SigmaQuad-II B2 RAM is always one address pin less than the
advertised index depth (e.g., the 2M x 8 has a 1M addressable
index).
Parameter Synopsis*
-200
-167
tKHKH
5.0 ns
6.0 ns
tKHQV
2.3 ns
2.5 ns


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Аналогичное описание - GS8180QV36BD-200

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