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GS8342Q36BD-333I датащи(PDF) 1 Page - GSI Technology |
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GS8342Q36BD-333I датащи(HTML) 1 Page - GSI Technology |
1 / 34 page GS8342Q08/09/18/36BD-357/333/300/250 36Mb SigmaQuad-IITM Burst of 2 SRAM 357 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 165-Bump BGA Commercial Temp Industrial Temp Rev: 1.02c 8/2017 1/34 © 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Features • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan • Pin-compatible with present 144 Mb devices • 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package available SigmaQuad™ Family Overview The GS8342Q08/09/18/36BD are built in compliance with the SigmaQuad-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 37,748,736-bit (36Mb) SRAMs. The GS8342Q08/09/18/36BD SigmaQuad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes The GS8342Q08/09/18/36BD SigmaQuad-II SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate the output register clock inputs quasi independently with the C and C clock inputs. C and C are also independent single-ended clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Each internal read and write operation in a SigmaQuad-II B2 RAM is two times wider than the device I/O bus. An input data bus de-multiplexer is used to accumulate incoming data before it is simultaneously written to the memory array. An output data multiplexer is used to capture the data produced from a single memory array read and then route it to the appropriate output drivers as needed. Therefore the address field of a SigmaQuad-II B2 RAM is always one address pin less than the advertised index depth (e.g., the 4M x 8 has an 2M addressable index). Parameter Synopsis -357 -333 -300 -250 tKHKH 2.8 ns 3.0 ns 3.3 ns 4.0 ns tKHQV 0.45 ns 0.45 ns 0.45 ns 0.45 ns |
Аналогичный номер детали - GS8342Q36BD-333I |
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Аналогичное описание - GS8342Q36BD-333I |
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