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GS81302Q08E-250I датащи(PDF) 7 Page - GSI Technology

номер детали GS81302Q08E-250I
подробное описание детали  144Mb SigmaQuadTM-II Burst of 2 SRAM
Download  33 Pages
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производитель  GSI [GSI Technology]
домашняя страница  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS81302Q08E-250I датащи(HTML) 7 Page - GSI Technology

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GS81302Q08/09/18/36E-300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04d 8/2017
7/33
© 2011, GSI Technology
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are
needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O
SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from
Separate I/O SRAMs can cut the RAM’s bandwidth in half.
SigmaQuad-II B2 SRAM DDR Read
The read port samples the status of the Address Input and R pins at each rising edge of K. A low on the Read Enable-bar pin, R,
begins a read cycle. Data can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied
high), and after the following rising edge of K with a rising edge of C (or by K if C and C are tied high). Clocking in a high on the
Read Enable-bar pin, R, begins a read port deselect cycle.
SigmaQuad-II B2 Double Data Rate SRAM Read First
Read A
NOP
Write B
Read C Write D
Read E Write F
Read G Write H
A
B
C
D
E
F
G
H
B
B+1
D
D+1
F
F+1
H
H+1
B
B+1
D
D+1
F
F+1
H
H+1
A
A+1
C
C+1
E
K
K
Address
R
W
BWx
D
C
C
Q
CQ
CQ


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