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AD7091R-5BRUZ датащи(PDF) 6 Page - Analog Devices

номер детали AD7091R-5BRUZ
подробное описание детали  4-Channel, I 2 C, Ultralow Power 12-Bit ADC in 20-Lead LFCSP/TSSOP
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домашняя страница  http://www.analog.com
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AD7091R-5BRUZ датащи(HTML) 6 Page - Analog Devices

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Data Sheet
AD7091R-5
Rev. 0 | Page 5 of 34
I2C TIMING SPECIFICATIONS
All values measured with the input filtering enabled. CB refers to the capacitive load on the bus line, with rise time and fall time measured
between 0.3 × VDRIVE and 0.7 × VDRIVE (see Figure 2). VDD = 2.7 V to 5.25 V, VDRIVE = 1.8 V to 5.25 V, VREF = 2.5 V internal/external, TA =
TMIN to TMAX, unless otherwise noted.
Table 2.
Limit at TMIN, TMAX
Parameter
Min
Typ
Max
Unit
Description
fSCL
100
kHz
Serial clock frequency, standard mode
400
kHz
Fast mode
t1
4
µs
SCL high time, standard mode
0.6
µs
Fast mode
t2
4.7
µs
SCL low time, standard mode
1.3
µs
Fast mode
t3
250
ns
Data setup time, standard mode
100
ns
Fast mode
t41
0
3.45
µs
Data hold time, standard mode
0
0.9
µs
Fast mode
t5
4.7
µs
Setup time for a repeated start condition, standard mode
0.6
µs
Fast mode
t6
4
µs
Hold time for a repeated start condition, standard mode
0.6
µs
Fast mode
t7
4.7
µs
Bus-free time between a stop and a start condition, standard mode
1.3
µs
Fast mode
t8
4
µs
Setup time for a stop condition, standard mode
0.6
µs
Fast mode
t9
1000
ns
Rise time of the SDA signal, standard mode
20 + 0.1CB
300
ns
Fast mode
t10
300
ns
Fall time of the SDA signal, standard mode
20 + 0.1CB
300
ns
Fast mode
t11
1000
ns
Rise time of the SCL signal, standard mode
20 + 0.1CB
300
ns
Fast mode
t11A
1000
ns
Rise time of the SCL signal after a repeated; not shown in Figure 2, standard mode
20 + 0.1CB
300
ns
Start condition and after an acknowledge bit, fast mode
t12
300
ns
Fall time of the SCL signal, standard mode
20 + 0.1CB
300
ns
Fast mode
tSP
0
50
ns
Pulse width of the suppressed spike; not shown in Figure 2, fast mode
tRESETPW
10
ns
RESET pulse width (see Figure 35)
tRESET_DELAY
50
ns
RESET pulse delay upon power-up (see Figure 35)
1
A device must provide a data hold time for SDA to bridge the undefined region of the SCL falling edge.
t6
t7
t2
t11
t4
t1
t12
t10
t5
t9
t6
t3
t8
SCL
S
SDA
S = START CONDITION
P = STOP CONDITION
P
P
S
Figure 2. 2-Wire Serial Interface Timing Diagram


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