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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9253BCPZRL7-105 датащи(PDF) 7 Page - Analog Devices |
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AD9253BCPZRL7-105 датащи(HTML) 7 Page - Analog Devices |
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7 / 41 page  AD9253 Data Sheet Rev. B | Page 6 of 40 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 4. Parameter1, 2 Temp Min Typ Max Unit CLOCK3 Input Clock Rate Full 10 1000 MHz Conversion Rate4 Full 10 80/105/125 MSPS Clock Pulse Width High (tEH) Full 6.25/4.76/4.00 ns Clock Pulse Width Low (tEL) Full 6.25/4.76/4.00 ns OUTPUT PARAMETERS3 Propagation Delay (tPD) Full 1.5 2.3 3.1 ns Rise Time (tR) (20% to 80%) Full 300 ps Fall Time (tF) (20% to 80%) Full 300 ps FCO Propagation Delay (tFCO) Full 1.5 2.3 3.1 ns DCO Propagation Delay (tCPD)5 Full tFCO + (tSAMPLE/16) ns DCO to Data Delay (tDATA)5 Full (tSAMPLE/16) − 300 (tSAMPLE/16) (tSAMPLE/16) + 300 ps DCO to FCO Delay (tFRAME)5 Full (tSAMPLE/16) − 300 (tSAMPLE/16) (tSAMPLE/16) + 300 ps Lane Delay (tLD) 90 ps Data to Data Skew (tDATA-MAX − tDATA-MIN) Full ±50 ±200 ps Wake-Up Time (Standby) 25°C 250 ns Wake-Up Time (Power-Down)6 25°C 375 μs Pipeline Latency Full 16 Clock cycles APERTURE Aperture Delay (tA) 25°C 1 ns Aperture Uncertainty (Jitter, tJ) 25°C 135 fs rms Out-of-Range Recovery Time 25°C 1 Clock cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Measured on standard FR-4 material. 3 Can be adjusted via the SPI. The conversion rate is the clock rate after the divider. 4 The maximum conversion rate is based on two-lane output mode. See the Digital Outputs and Timing section for the maximum conversion rate in one-lane output mode. 5 tSAMPLE/16 is based on the number of bits in two LVDS data lanes. tSAMPLE = 1/fS. 6 Wake-up time is defined as the time required to return to normal operation from power-down mode. TIMING SPECIFICATIONS Table 5. Parameter Description Limit Unit SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK+ setup time 1.2 ns min tHSYNC SYNC to rising edge of CLK+ hold time −0.2 ns min SPI TIMING REQUIREMENTS See Figure 74 tDS Setup time between the data and the rising edge of SCLK 2 ns min tDH Hold time between the data and the rising edge of SCLK 2 ns min tCLK Period of the SCLK 40 ns min tS Setup time between CSB and SCLK 2 ns min tH Hold time between CSB and SCLK 2 ns min tHIGH SCLK pulse width high 10 ns min tLOW SCLK pulse width low 10 ns min tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 74) 10 ns min tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 74) 10 ns min |
Аналогичный номер детали - AD9253BCPZRL7-105 |
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Аналогичное описание - AD9253BCPZRL7-105 |
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