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AD7992BRM-1 датащи(PDF) 10 Page - Analog Devices |
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AD7992BRM-1 датащи(HTML) 10 Page - Analog Devices |
10 / 21 page AD7992 –10– REV. PrH PRELIMINARYTECHNICAL DATA CIRCUIT INFORMATION The AD7992 is a fast, micro-power, 12-bit, single supply, 2 Channel A/D converter. The part can be operated from a 2.7 V to 5.5 V supply. The AD7992 provides the user with a 2-channel multi- plexer, an on-chip track/hold, A/D converter, an on-chip oscillator, internal data registers and an I 2C compatible serial interface, all housed in a 10-lead MSOP package, which offers the user considerable space saving advantages over alternative solutions. An external reference is re- quired by the AD7992, and this reference can be in the range of 1.2 V to VDD. The AD7992 will normally remain in a shutdown state while not converting. When supplies are first applied the part will come up in a power-down state. Power-up is intitiated prior to a conversion and the device returns to power-down upon completion of the conversion. Conver- sions can be initiated on the AD7992 by either pulsing the CONVST signal, using an automatic cycling mode or using a mode where wake-up and conversion occur during the read function ( see modes of Operation section). On completion of a conversion, the AD7992 will enter shut- down mode again. This automatic shutdown feature allows power saving between conversions. This means any read or write operations across the serial interface can occur while the device is in shutdown. The serial interface is I 2C com- patible. ADC TRANSFER FUNCTION The output coding of the AD7992 is straight binary. The designed code transitions occur at successive integer LSB values (i.e., 1LSB, 2LSBs, etc.). The LSB size for the AD7992 is = REFIN/4096 . The ideal transfer characteris- tic for the AD7992 is shown in Figure 4 below. CONVERTER OPERATION The AD7992 is a successive approximation analog-to - digital converter based around a charge redistribution DAC. Figures 2 and 3 show simplified schematics of the ADC. Figure 2 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in position A, the com- parator is held in a balanced condition and the sampling capacitor acquires the signal on VIN. When the ADC starts a conversion, see Figure 3, SW2 will open and SW1 will move to position B causing the comparator to become unbalanced. The Control Logic and the Charge Redistribution DAC are used to add and subtract fixed amounts of charge from the sampling ca- pacitor to bring the comparator back into a balanced con- dition. When the comparator is rebalanced the conversion is complete. The Control Logic generates the ADC out- put code. Figure 4 shows the ADC transfer function. Figure 2. ADC Acquisition Phase Figure 3. ADC Conversion Phase Figure 4. AD7992 Transfer Characteristic TYPICAL CONNECTION DIAGRAM Figure 5 shows the typical connection diagram for the AD7992. In Figure 5 the Address Select pin, AS, is tied to VDD, however AS can also be either tied to GND or left floating, allowing the user to select up to three AD7992 devices on the same serial bus. An external refer- ence must be applied to the AD7992. This reference can be in the range of 1.2 V to VDD. A precision reference like the REF 19X family or the ADR421 can be used to supply the Reference Voltage to the ADC. SDA and SCL form the two-wire I 2C/SMBus compatible interface. External Pull up resistors should be added to the SDA and SCL bus lines. The AD7992-0 supports Standard and Fast I2C Interface Modes. While the AD7992-1 supports Standard, Fast and Highspeed I 2C Interface Modes. Therefore if operating the AD7992 in either Standard or Fast Mode, five AD7992 (3 x AD7992-0 and 2 x AD7992-1 or 2 x AD7992-0 and 3 x AD7992-1) parts can be connected to the bus. When operating the AD7992 in Hs-Mode then up to three AD7992-1 can be connected to the bus. Wake-up from power-down prior to a conversion is ap- proximately 1µs while conversion time is approximately 2µs. The AD7992 enters power-down mode again after each conversion, this automatic powerdown feature will be useful in applications where power consumption is of con- cern. CAPACITIVE DAC V IN COMPARATOR CONTROL LOGIC SW1 A B SW2 AGND CAPACITIVE DAC V IN COMPARATOR CONTROL LOGIC SW1 A B SW2 AGND 000...000 ANALOG INPUT 0 V TO REFIN 111...111 000...001 000...010 111...110 111...000 011...111 AGND +1 LSB +REFIN -1LSB 1LSB = REFIN/4096 |
Аналогичный номер детали - AD7992BRM-1 |
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Аналогичное описание - AD7992BRM-1 |
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