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CDCU877ZQL датащи(PDF) 5 Page - Texas Instruments |
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CDCU877ZQL датащи(HTML) 5 Page - Texas Instruments |
5 / 17 page CDCU877/CDCU877A 1.8V PHASE LOCK LOOP CLOCK DRIVER SCAS688A − JUNE 2003 − REVISED JANUARY 2004 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VDDQ or AVDD −0.5 V to 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage range, VI (see Notes 1 and 2) −0.5 V to VDDQ + 0.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output voltage range, VO (see Notes 1 and 2) −0.5 V to VDDQ + 0.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input clamp current, IIK (VI < 0 or VI > VDDQ) ±50 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output clamp voltage, IOK (VO < 0 or VO > VDDQ) ±50 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous output current, IO (VO = 0 to VDDQ) ±50 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous current through each VDDQ or GND ±100 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, TSTG −65 °C to 150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed 2. This value is limited to 2.5 V maximum. recommended operating conditions MIN NOM MAX UNIT VDDQ Output supply voltage 1.7 1.8 1.9 V AVDD Supply voltage See Note 1 VDDQ VIL Low-level input voltage (see Note 2) OE, OS 0.35 × VDDQ V VIH High-level input voltage (see Note 2) CK, CK 0.65 × VDDQ V IOH High-level output current (see Figure 2) −9 mA IOL Low-level output current (see Figure 2) 9 mA VIX Input differential-pair cross voltage (VDDQ/2)−0.15 (VDDQ/2)+0.15 V VI Input voltage level −0.3 VDDQ+0.3 V VID Input differential voltage (see Note 2 and Figure 9) DC 0.3 VDDQ+0.4 V VID Input differential voltage (see Note 2 and Figure 9) AC 0.6 VDDQ+0.4 V TA Operating free-air temperature −40 85 °C NOTES: 1. The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, VDDQ remains within the recommended operating conditions and no timing parameters are ensured. 2. VID is the magnitude of the difference between the input level on CK and the input level on CK, see Figure 9 for definition. The CK and CK VIH and VIL limits define the dc low and high levels for the logic detect state. |
Аналогичный номер детали - CDCU877ZQL |
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Аналогичное описание - CDCU877ZQL |
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