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LFC789D25CD датащи(PDF) 6 Page - Texas Instruments |
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LFC789D25CD датащи(HTML) 6 Page - Texas Instruments |
6 / 11 page LFC789D25 DUAL LINEAR FET CONTROLLER SLLS565B − MARCH 2003 − REVISED SEPTEMBER 2004 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION MOSFET SELECTION: BENEFITS OF NMOS PASS ELEMENTS REVISITED A great benefit of having an external pass element is that the control circuitry can be powered by a separate supply (VCC), other than the one used as the input to the pass element (VPWR). This feature allows the use of an NMOS pass element, which requires a positive VGS > VT for operation. With a separate VCC pin to the controller, the voltage at the gate of the NMOS readily can exceed the voltage at the drain; thus, VGS easily can exceed VDS + VT, allowing the NMOS to operate in the triode region (VDS ≥ VGS − VT). In the triode region, VDS can be very small, thus achieving very low dropout. The external NMOS selected for the pass transistor has significant impact on the overall characteristics of the regulator, as discussed in the following paragraphs. D Maximum output current A benefit of an external pass element is that the designer can size the NMOS to easily sustain the maximum IOUT expected. This allows great flexibility, along with cost and space savings, because each regulator has its pass element tailored to its individual needs. In addition, using an NMOS pass element allows for smaller size (and subsequently, lower cost) than a PMOS element for the same current-carrying ability. D Dropout Choosing an NMOS with very low RDS(on) characteristics provides the regulator with very low dropout because dropout will be ∼IOUT × RDS(on). This lower dropout also results in better efficiency and lower heat dissipation in the pass element for a given IOUT. D Maximum programmable output voltage and NMOS threshold voltage, VT The maximum output voltage that can be regulated by the programmable regulator depends on the device’s power supply (VCC) and threshold voltage (VT) of the NMOS. With the drive voltage tied to the gate and VOUT connected to the source of the NMOS, a minimum VGS = VT must be maintained in order to maintain the n-channel inversion layer. The maximum VOUT is calculated as follows: VOUT = VS = VG − VT With VCC = 12 V and a corresponding worst-case gate drive voltage of 9 V, the highest achievable VOUT = 9 V − VT. D Stability A quality of the old npn regulators was their inherent stability under almost any type of load conditions and output capacitors. An NMOS regulator has the same benefit. Thus, capacitor selection and equivalent-series-resistance (ESR) values are not needed for stability, but still should be chosen properly for best transient response (see below). capacitor selection Cout: Although a minimum capacitance is not needed for stability with an NMOS pass device, higher capacitance values improve transient response. In addition, low-ESR capacitors also help transient response. Tantalum or aluminum electrolytics can be used for bulk capacitances, while ceramic bypass capacitors can be used to decouple high-frequency transients due to their low ESL (equivalent series inductance). Cin: Input capacitors placed at the drain of the NMOS pass transistor (VPWR) help improve the overall transient response by suppressing surges in VPWR during fast load changes. Low-ESR tantalum or aluminum electrolytic capacitors can be used; higher capacitance values improve transient response. A 0.1- µF ceramic capacitor can be placed at the VCC pin of the LFC789D25 to provide bypassing. |
Аналогичный номер детали - LFC789D25CD |
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Аналогичное описание - LFC789D25CD |
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