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AMC1106E05, AMC1106M05

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SBAS789 – OCTOBER 2017

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7.10 Timing Requirements

over operating ambient temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

CLKIN clock frequency

4.5 V

≤ AVDD ≤ 5.5 V

5

21

MHz

3.0 V

≤ AVDD ≤ 5.5 V

5

20

CLKIN clock period,

see Figure 1

4.5 V

≤ AVDD ≤ 5.5 V

47.6

200

ns

3.0 V

≤ AVDD ≤ 5.5 V

50

200

CLKIN clock high time, see Figure 1

20

25

120

ns

CLKIN clock low time, see Figure 1

20

25

120

ns

(1)

The output of the Manchester encoded versions of the AMC1106E05 can change with every edge of CLKIN with a typical delay of 6 ns;

see the Manchester Coding Feature section for additional details.

7.11 Switching Characteristics

over operating ambient temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DOUT hold time after rising edge

of CLKIN, see Figure 1

3.5

ns

Rising edge of CLKIN to DOUT

valid delay, see Figure 1

15

ns

DOUT rise time, see Figure 1

10% to 90%, 2.7 V

≤ DVDD ≤ 3.6 V,

0.8

3.5

ns

10% to 90%, 4.5 V

≤ DVDD ≤ 5.5 V,

1.8

3.9

DOUT fall time, see Figure 1

90% to 10%, 2.7 V

≤ DVDD ≤ 3.6 V,

0.8

3.5

ns

90% to 10%, 4.5 V

≤ DVDD ≤ 5.5 V,

1.8

3.9

Interface startup time,

see Figure 2

DVDD at 2.7 V (min) to DOUT valid with

AVDD

≥ 3.0 V

32

32

Analog startup time,

see Figure 2

AVDD step to 3.0 V with DVDD

≥ 2.7 V,

0.1% settling

0.5

ms