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AM3352BZCZD80 датащи(PDF) 3 Page - Texas Instruments

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номер детали AM3352BZCZD80
подробное описание детали  Sitara Processors
Download  253 Pages
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI1 - Texas Instruments

AM3352BZCZD80 датащи(HTML) 3 Page - Texas Instruments

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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
www.ti.com
SPRS717J – OCTOBER 2011 – REVISED APRIL 2016
Submit Documentation Feedback
Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351
Device Overview
Copyright © 2011–2016, Texas Instruments Incorporated
Programmable High-Quality Image Anti-
Aliasing
Fully Virtualized Memory Addressing for OS
Operation in a Unified Memory Architecture
– LCD Controller
Up to 24-Bit Data Output; 8 Bits per Pixel
(RGB)
Resolution up to 2048 × 2048 (With
Maximum 126-MHz Pixel Clock)
Integrated LCD Interface Display Driver
(LIDD) Controller
Integrated Raster Controller
Integrated DMA Engine to Pull Data from the
External Frame Buffer Without Burdening the
Processor via Interrupts or a Firmware Timer
512-Word Deep Internal FIFO
Supported Display Types:
Character Displays - Uses LIDD
Controller to Program these Displays
Passive Matrix LCD Displays - Uses LCD
Raster Display Controller to Provide
Timing and Data for Constant Graphics
Refresh to a Passive Display
Active Matrix LCD Displays - Uses
External Frame Buffer Space and the
Internal DMA Engine to Drive Streaming
Data to the Panel
– 12-Bit Successive Approximation Register
(SAR) ADC
200K Samples per Second
Input can be Selected from any of the Eight
Analog Inputs Multiplexed Through an 8:1
Analog Switch
Can be Configured to Operate as a 4-Wire,
5-Wire, or 8-Wire Resistive Touch Screen
Controller (TSC) Interface
– Up to Three 32-Bit eCAP Modules
Configurable as Three Capture Inputs or
Three Auxiliary PWM Outputs
– Up to Three Enhanced High-Resolution PWM
Modules (eHRPWMs)
Dedicated 16-Bit Time-Base Counter With
Time and Frequency Controls
Configurable as Six Single-Ended, Six Dual-
Edge Symmetric, or Three Dual-Edge
Asymmetric Outputs
– Up to Three 32-Bit Enhanced Quadrature
Encoder Pulse (eQEP) Modules
• Device Identification
– Contains Electrical Fuse Farm (FuseFarm) of
Which Some Bits are Factory Programmable
Production ID
Device Part Number (Unique JTAG ID)
Device Revision (Readable by Host ARM)
• Debug Interface Support
– JTAG and cJTAG for ARM (Cortex-A8 and
PRCM), PRU-ICSS Debug
– Supports Device Boundary Scan
– Supports IEEE 1500
• DMA
– On-Chip Enhanced DMA Controller (EDMA) has
Three Third-Party Transfer Controllers (TPTCs)
and One Third-Party Channel Controller
(TPCC), Which Supports up to 64
Programmable Logical Channels and Eight
QDMA Channels. EDMA is Used for:
Transfers to and from On-Chip Memories
Transfers to and from External Storage
(EMIF, GPMC, Slave Peripherals)
• Inter-Processor Communication (IPC)
– Integrates Hardware-Based Mailbox for IPC and
Spinlock for Process Synchronization Between
Cortex-A8, PRCM, and PRU-ICSS
Mailbox Registers that Generate Interrupts
Four Initiators (Cortex-A8, PRCM, PRU0,
PRU1)
Spinlock has 128 Software-Assigned Lock
Registers
• Security
– Crypto Hardware Accelerators (AES, SHA,
RNG)
– Secure Boot
• Boot Modes
– Boot Mode is Selected Through Boot
Configuration Pins Latched on the Rising Edge
of the PWRONRSTn Reset Input Pin
• Packages:
– 298-Pin S-PBGA-N298 Via Channel Package
(ZCE Suffix), 0.65-mm Ball Pitch
– 324-Pin S-PBGA-N324 Package
(ZCZ Suffix), 0.80-mm Ball Pitch


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