 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
SI4123G датащи(PDF) 8 Page - Silicon Laboratories |
|
||||||||||||||||||||||||||||||
SI4123G датащи(HTML) 8 Page - Silicon Laboratories |
|
|
8 / 32 page  Si 41 33 G 8 Rev. 1.1 Table 5. RF and IF Synthesizer Characteristics (VDD = 2.7 to 3.6 V, TA = –20 to 85°C) Parameter1 Symbol Test Condition Min Typ Max Unit XIN Input Frequency f REF —13 — MHz Reference Amplifier Sensitivity V REF 0.5 — VDD +0.3 VPP Phase Detector Update Frequency fφ fφ = fREF/R 200 KHz RF1 Center Frequency Range fCEN 947 — 1720 MHz RF2 Center Frequency Range fCEN 789 — 1429 MHz IF VCO Center Frequency fCEN 526 — 952 MHz Tuning Range from fCEN Note: LEXT ±10% –5 — 5 % RF1 VCO Pushing Open loop — 0.5 — MHz/V RF2 VCO Pushing — 0.4 — MHz/V IF VCO Pushing — 0.3 — MHz/V RF1 VCO Pulling VSWR = 2:1, all phases, open loop —0.4 — MHzPP RF2 VCO Pulling — 0.1 — MHzPP IF VCO Pulling — 0.1 — MHzPP RF1 Phase Noise 1 MHz offset — –132 — dBc/Hz 3 MHz offset — –142 — dBc/Hz RF1 Integrated Phase Error 100 Hz to 100 kHz — 0.9 — deg rms RF2 Phase Noise 1 MHz offset — –134 — dBc/Hz 3 MHz offset — –144 — dBc/Hz RF2 Integrated Phase Error 100 Hz to 100 kHz — 0.7 — deg rms IF Phase Noise 100 kHz offset — –117 — dBc/Hz IF Integrated Phase Error 100 Hz to 100 kHz — 0.4 — deg rms RF1 Harmonic Suppression Second Harmonic — –26 — dBc RF2 Harmonic Suppression — –26 — dBc IF Harmonic Suppression — –26 — dBc RFOUT Power Level ZL = 50 Ω –7 –2 1 dBm IFOUT Power Level ZL = 50 Ω –8 –6 –1 dBm RF1 Reference Spurs Offset = 200 kHz — –70 — dBc Offset = 400 kHz — –75 — dBc Offset = 600 kHz — –80 — dBc R F2 Reference Spurs Offset = 200 kHz — –75 — dBc Offset = 400 kHz — –80 — dBc Offset = 600 kHz — –80 — dBc Power Up Request to Synthesizer Ready Time, RF1, RF2, IF2 tpup Figures 4, 5 — 140 — µs Power Down Request to Synthesizer Off Time3 t pdn Figures 4, 5 — — 100 ns Notes: 1. RF1 = 1.55 GHz, RF2 = 1.2 GHz, IF = 550 MHz for all parameters unless otherwise noted. 2. From power up request (PWDNB ↑ or SENB↑ during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF synthesizers ready (settled to within 0.1 ppm frequency error). Typical settling time to 5 degrees phase error is 120 µs. 3. From power down request (PWDNB ↓, or SENB↑ during a write of 0 to bits PDIB and PDRB in Register 2) to supply current equal to IPWDN. |
Аналогичный номер детали - SI4123G |
|
Аналогичное описание - SI4123G |
|
|
ссылки URL |
| Конфиденциальность |
| ALLDATASHEETRU.COM |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
