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MT9P401 датащи(PDF) 11 Page - ON Semiconductor

номер детали MT9P401
подробное описание детали  1/2.5-Inch 5 Mp CMOS Digital Image Sensor
Download  45 Pages
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производитель  ONSEMI [ON Semiconductor]
домашняя страница  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MT9P401 датащи(HTML) 11 Page - ON Semiconductor

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MT9P401
CONFIDENTIAL AND PROPRIETARY
NOT FOR PUBLIC RELEASE
www.onsemi.com
11
SERIAL BUS DESCRIPTION
Registers are written to and read from the MT9P401
through the two−wire serial interface bus. The MT9P401 is
a serial interface slave and is controlled by the serial clock
(SCLK), which is driven by the serial interface master. Data
is transferred into and out of the MT9P401 through the serial
data (SDATA) line. The SDATA line is pulled up to VDD_IO
off−chip by a 1.5 k
Ω resistor. Either the slave or master
device can pull the SDATA line LOW—the serial interface
protocol determines which device is allowed to pull the
SDATA line down at any given time.
Protocol
The two-wire serial defines several different transmission
codes, as follows:
1. a start bit
2. the slave device 8-bit address
3. an (a no) acknowledge bit
4. an 8-bit message
5. a stop bit
Sequence
A typical READ or WRITE sequence begins by the
master sending a start bit. After the start bit, the master sends
the slave device’s 8−bit address. The last bit of the address
determines if the request is a READ or a WRITE, where a
“0” indicates a WRITE and a “1” indicates a READ. The
slave device acknowledges its address by sending an
acknowledge bit back to the master.
If the request is a WRITE, the master then transfers the
8−bit register address to which a WRITE should take place.
The slave sends an acknowledge bit to indicate that the
register address has been received. The master then transfers
the data 8 bits at a time, with the slave sending an
acknowledge bit after each 8 bits. The MT9P401 uses 16−bit
data for its internal registers, thus requiring two 8−bit
transfers to write to one register. After 16 bits are transferred,
the register address is automatically incremented, so that the
next 16 bits are written to the next register address. The
master stops writing by sending a start or stop bit.
A typical READ sequence is executed as follows. First the
master sends the write−mode slave address and 8−bit
register address, just as in the WRITE request. The master
then sends a start bit and the read−mode slave address. The
master then clocks out the register data 8 bits at a time. The
master sends an acknowledge bit after each 8−bit transfer.
The register address is automatically−incremented after
every 16 bits is transferred. The data transfer is stopped
when the master sends a no−acknowledge bit.
Bus Idle State
The bus is idle when both the data and clock lines are
HIGH. Control of the bus is initiated with a start bit, and the
bus is released with a stop bit. Only the master can generate
the start and stop bits.
Start Bit
The start bit is defined as a HIGH−to−LOW transition of
the data line while the clock line is HIGH.
Stop Bit
The stop bit is defined as a LOW−to−HIGH transition of
the data line while the clock line is HIGH.
Slave Address
The 8−bit address of a two−wire serial interface device
consists of 7 bits of address and 1 bit of direction. A “0” in
the LSB (least significant bit) of the address indicates write
mode (0xBA), and a “1” indicates read mode (0xBB).
Data Bit Transfer
One data bit is transferred during each clock pulse. The
serial interface clock pulse is provided by the master. The
data must be stable during the HIGH period of the two−wire
serial interface clock−it can only change when the serial
clock is LOW. Data is transferred 8 bits at a time, followed
by an acknowledge bit.
Acknowledge Bit
The master generates the acknowledge clock pulse. The
transmitter (which is the master when writing, or the slave
when reading) releases the data line, and the receiver
indicates an acknowledge bit by pulling the data line LOW
during the acknowledge clock pulse.
No-Acknowledge Bit
The no−acknowledge bit is generated when the data line
is not pulled down by the receiver during the acknowledge
clock pulse. A no−acknowledge bit is used to terminate a
read sequence.


Аналогичный номер детали - MT9P401_17

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